From 80333573c7ec12be8df87ebf9563fb868f46221e Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 15 Oct 2019 18:07:48 +0300 Subject: [PATCH] ad_fmclidar1_ebz/zcu102: Fix SYSREF input delay constraint Add one clock cycle input delay for the SYSREF input, to compensate the high propegation delay of device_clk_BUFG. --- projects/ad_fmclidar1_ebz/zcu102/system_constr.xdc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/projects/ad_fmclidar1_ebz/zcu102/system_constr.xdc b/projects/ad_fmclidar1_ebz/zcu102/system_constr.xdc index 07c4215b5..0832a9c4c 100644 --- a/projects/ad_fmclidar1_ebz/zcu102/system_constr.xdc +++ b/projects/ad_fmclidar1_ebz/zcu102/system_constr.xdc @@ -98,9 +98,8 @@ set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports afe_adc_sd create_clock -period 4.000 -name rx_device_clk [get_ports rx_device_clk_p] create_clock -period 4.000 -name rx_ref_clk [get_ports rx_ref_clk_p] -# SYSREF is in phase with the device clock +# SYSREF is edge-aligned rising edge source synchronous input -set_input_delay -clock [get_clocks rx_device_clk] -rise -max 0.200 [get_ports -regexp -filter { NAME =~ ".*sysref.*" && DIRECTION == "IN" }] -set_input_delay -clock [get_clocks rx_device_clk] -rise -min -0.200 [get_ports -regexp -filter { NAME =~ ".*sysref.*" && DIRECTION == "IN" }] -set_property IOBDELAY NONE [get_cells -hierarchical -regexp -filter { NAME =~ ".*sysref_r_reg"}] +set_input_delay -clock [get_clocks rx_device_clk] [get_property PERIOD [get_clocks rx_device_clk]] \ + [get_ports -regexp -filter { NAME =~ ".*sysref.*" && DIRECTION == "IN" }]