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ad_fmclidar1_ebz/zcu102: Fix SYSREF input delay constraint 

Add one clock cycle input delay for the SYSREF input,
to compensate the high propegation delay of device_clk_BUFG.
main
Istvan Csomortani 2019-10-15 18:07:48 +03:00 committed by István Csomortáni
parent 03bec4b49c
commit 80333573c7
1 changed files with 3 additions and 4 deletions
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projects/ad_fmclidar1_ebz/zcu102/system_constr.xdc
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@ -98,9 +98,8 @@ set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports afe_adc_sd
create_clock -period 4.000 -name rx_device_clk [get_ports rx_device_clk_p]
create_clock -period 4.000 -name rx_ref_clk [get_ports rx_ref_clk_p]
# SYSREF is in phase with the device clock
# SYSREF is edge-aligned rising edge source synchronous input
set_input_delay -clock [get_clocks rx_device_clk] -rise -max 0.200 [get_ports -regexp -filter { NAME =~ ".*sysref.*" && DIRECTION == "IN" }]
set_input_delay -clock [get_clocks rx_device_clk] -rise -min -0.200 [get_ports -regexp -filter { NAME =~ ".*sysref.*" && DIRECTION == "IN" }]
set_property IOBDELAY NONE [get_cells -hierarchical -regexp -filter { NAME =~ ".*sysref_r_reg"}]
set_input_delay -clock [get_clocks rx_device_clk] [get_property PERIOD [get_clocks rx_device_clk]] \
[get_ports -regexp -filter { NAME =~ ".*sysref.*" && DIRECTION == "IN" }]