xfer-logic: stretch toggles to allow capture
parent
890bb1da75
commit
8050a14bd8
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@ -74,6 +74,9 @@ module up_xfer_cntrl (
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// internal registers
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// internal registers
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reg up_xfer_state_m1 = 'd0;
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reg up_xfer_state_m2 = 'd0;
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reg up_xfer_state = 'd0;
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reg [ 5:0] up_xfer_count = 'd0;
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reg [ 5:0] up_xfer_count = 'd0;
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reg up_xfer_done = 'd0;
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reg up_xfer_done = 'd0;
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reg up_xfer_toggle = 'd0;
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reg up_xfer_toggle = 'd0;
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@ -81,24 +84,34 @@ module up_xfer_cntrl (
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reg d_xfer_toggle_m1 = 'd0;
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reg d_xfer_toggle_m1 = 'd0;
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reg d_xfer_toggle_m2 = 'd0;
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reg d_xfer_toggle_m2 = 'd0;
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reg d_xfer_toggle_m3 = 'd0;
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reg d_xfer_toggle_m3 = 'd0;
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reg d_xfer_toggle = 'd0;
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reg [DW:0] d_data_cntrl = 'd0;
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reg [DW:0] d_data_cntrl = 'd0;
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// internal signals
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// internal signals
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wire up_xfer_enable_s;
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wire d_xfer_toggle_s;
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wire d_xfer_toggle_s;
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// device control transfer
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// device control transfer
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assign up_xfer_enable_s = up_xfer_state ^ up_xfer_toggle;
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always @(negedge up_rstn or posedge up_clk) begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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if (up_rstn == 1'b0) begin
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up_xfer_state_m1 <= 'd0;
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up_xfer_state_m2 <= 'd0;
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up_xfer_state <= 'd0;
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up_xfer_count <= 'd0;
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up_xfer_count <= 'd0;
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up_xfer_done <= 'd0;
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up_xfer_done <= 'd0;
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up_xfer_toggle <= 'd0;
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up_xfer_toggle <= 'd0;
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up_xfer_data <= 'd0;
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up_xfer_data <= 'd0;
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end else begin
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end else begin
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up_xfer_state_m1 <= d_xfer_toggle;
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up_xfer_state_m2 <= up_xfer_state_m1;
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up_xfer_state <= up_xfer_state_m2;
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up_xfer_count <= up_xfer_count + 1'd1;
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up_xfer_count <= up_xfer_count + 1'd1;
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up_xfer_done <= (up_xfer_count == 6'd1) ? 1'b1 : 1'b0;
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up_xfer_done <= (up_xfer_count == 6'd1) ? ~up_xfer_enable_s : 1'b0;
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if (up_xfer_count == 6'd1) begin
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if ((up_xfer_count == 6'd1) && (up_xfer_enable_s == 1'b0)) begin
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up_xfer_toggle <= ~up_xfer_toggle;
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up_xfer_toggle <= ~up_xfer_toggle;
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up_xfer_data <= up_data_cntrl;
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up_xfer_data <= up_data_cntrl;
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end
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end
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@ -112,11 +125,13 @@ module up_xfer_cntrl (
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d_xfer_toggle_m1 <= 'd0;
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d_xfer_toggle_m1 <= 'd0;
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d_xfer_toggle_m2 <= 'd0;
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d_xfer_toggle_m2 <= 'd0;
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d_xfer_toggle_m3 <= 'd0;
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d_xfer_toggle_m3 <= 'd0;
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d_xfer_toggle <= 'd0;
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d_data_cntrl <= 'd0;
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d_data_cntrl <= 'd0;
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end else begin
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end else begin
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d_xfer_toggle_m1 <= up_xfer_toggle;
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d_xfer_toggle_m1 <= up_xfer_toggle;
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d_xfer_toggle_m2 <= d_xfer_toggle_m1;
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d_xfer_toggle_m2 <= d_xfer_toggle_m1;
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d_xfer_toggle_m3 <= d_xfer_toggle_m2;
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d_xfer_toggle_m3 <= d_xfer_toggle_m2;
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d_xfer_toggle <= d_xfer_toggle_m3;
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if (d_xfer_toggle_s == 1'b1) begin
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if (d_xfer_toggle_s == 1'b1) begin
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d_data_cntrl <= up_xfer_data;
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d_data_cntrl <= up_xfer_data;
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end
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end
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