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altera/common- ad_serdes_clk

main
Rejeesh Kutty 2016-10-27 09:40:45 -04:00
parent 50552ce7d6
commit 8107514dde
2 changed files with 158 additions and 190 deletions
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229
library/altera/alt_serdes/alt_serdes_hw.tcl
View File

@ -38,63 +38,12 @@ set_parameter_property CLKIN_FREQUENCY UNITS None
set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz"
set_parameter_property CLKIN_FREQUENCY HDL_PARAMETER false
# these paramteres are needed just because of cross-platform requirments
# are NOT used in the core
add_parameter DEVICE_FAMILY STRING
set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
set_parameter_property DEVICE_FAMILY ENABLED false
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER false
add_parameter MMCM_OR_BUFR_N INTEGER 0
set_parameter_property MMCM_OR_BUFR_N DEFAULT_VALUE 0
set_parameter_property MMCM_OR_BUFR_N DISPLAY_NAME MMCM_OR_BUFIO_N
set_parameter_property MMCM_OR_BUFR_N TYPE INTEGER
set_parameter_property MMCM_OR_BUFR_N UNITS None
set_parameter_property MMCM_OR_BUFR_N HDL_PARAMETER false
add_parameter MMCM_CLKIN_PERIOD FLOAT 0
set_parameter_property MMCM_CLKIN_PERIOD DEFAULT_VALUE 1.667
set_parameter_property MMCM_CLKIN_PERIOD DISPLAY_NAME MMCM_CLKIN_PERIOD
set_parameter_property MMCM_CLKIN_PERIOD TYPE INTEGER
set_parameter_property MMCM_CLKIN_PERIOD UNITS None
set_parameter_property MMCM_CLKIN_PERIOD HDL_PARAMETER false
add_parameter MMCM_VCO_DIV INTEGER 0
set_parameter_property MMCM_VCO_DIV DEFAULT_VALUE 2
set_parameter_property MMCM_VCO_DIV DISPLAY_NAME MMCM_VCO_DIV
set_parameter_property MMCM_VCO_DIV TYPE INTEGER
set_parameter_property MMCM_VCO_DIV UNITS None
set_parameter_property MMCM_VCO_DIV HDL_PARAMETER false
add_parameter MMCM_VCO_MUL INTEGER 0
set_parameter_property MMCM_VCO_MUL DEFAULT_VALUE 4
set_parameter_property MMCM_VCO_MUL DISPLAY_NAME MMCM_VCO_MUL
set_parameter_property MMCM_VCO_MUL TYPE INTEGER
set_parameter_property MMCM_VCO_MUL UNITS None
set_parameter_property MMCM_VCO_MUL HDL_PARAMETER false
add_parameter MMCM_CLK0_DIV INTEGER 0
set_parameter_property MMCM_CLK0_DIV DEFAULT_VALUE 2
set_parameter_property MMCM_CLK0_DIV DISPLAY_NAME MMCM_CLK0_DIV
set_parameter_property MMCM_CLK0_DIV TYPE INTEGER
set_parameter_property MMCM_CLK0_DIV UNITS None
set_parameter_property MMCM_CLK0_DIV HDL_PARAMETER false
add_parameter MMCM_CLK1_DIV INTEGER 0
set_parameter_property MMCM_CLK1_DIV DEFAULT_VALUE 8
set_parameter_property MMCM_CLK1_DIV DISPLAY_NAME MMCM_CLK1_DIV
set_parameter_property MMCM_CLK1_DIV TYPE INTEGER
set_parameter_property MMCM_CLK1_DIV UNITS None
set_parameter_property MMCM_CLK1_DIV HDL_PARAMETER false
proc p_alt_serdes {} {
set m_mode [get_parameter_value "MODE"]
@ -105,6 +54,7 @@ proc p_alt_serdes {} {
set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))]
set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)]
set m_ls_phase 22.5
set m_ld_phase 315.0
set m_ld_duty_cycle 12.5
@ -114,98 +64,54 @@ proc p_alt_serdes {} {
set m_ld_duty_cycle 25.0
}
if {$m_mode == "CLK"} {
## arria 10, serdes clock, data-in and data-out
if {$m_device_family == "Arria 10"} {
add_instance alt_serdes_pll altera_iopll
set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
add_interface rst reset sink
set_interface_property rst EXPORT_OF alt_serdes_pll.reset
add_interface ref_clk clock sink
set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
add_interface locked conduit end
set_interface_property locked EXPORT_OF alt_serdes_pll.locked
add_interface hs_phase conduit end
set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
add_interface hs_clk conduit end
set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk
add_interface loaden conduit end
set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden
add_interface ls_clk clock source
set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
if {($m_mode == "CLK") && ($m_device_family == "Arria 10")} {
add_instance alt_serdes_pll_reconfig altera_pll_reconfig
add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
add_interface drp_clk clock sink
set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
add_interface drp_rst reset sink
set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
add_interface pll_reconfig avalon slave
set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
}
add_instance alt_serdes_pll altera_iopll
set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
add_interface rst reset sink
set_interface_property rst EXPORT_OF alt_serdes_pll.reset
add_interface ref_clk clock sink
set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
add_interface locked conduit end
set_interface_property locked EXPORT_OF alt_serdes_pll.locked
add_interface hs_phase conduit end
set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
add_interface hs_clk conduit end
set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk
add_interface loaden conduit end
set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden
add_interface ls_clk clock source
set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
if {$m_device_family == "Cyclone V"} {
add_instance alt_serdes_pll altera_pll
set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3}
set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
add_interface rst reset sink
set_interface_property rst EXPORT_OF alt_serdes_pll.reset
add_interface ref_clk clock sink
set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
add_interface locked conduit end
set_interface_property locked EXPORT_OF alt_serdes_pll.locked
add_interface hs_phase conduit end
set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
add_interface hs_clk clock source
set_interface_property hs_clk EXPORT_OF alt_serdes_pll.outclk0
add_interface loaden clock source
set_interface_property loaden EXPORT_OF alt_serdes_pll.outclk1
add_interface ls_clk clock source
set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
add_instance alt_serdes_pll_reconfig altera_pll_reconfig
add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
add_interface drp_clk clock sink
set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
add_interface drp_rst reset sink
set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
add_interface pll_reconfig avalon slave
set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
}
add_instance alt_serdes_pll_reconfig altera_pll_reconfig
add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
add_interface drp_clk clock sink
set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
add_interface drp_rst reset sink
set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
add_interface pll_reconfig avalon slave
set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
}
if {$m_mode == "IN"} {
if {($m_mode == "IN") && ($m_device_family == "Arria 10")} {
add_instance alt_serdes_in altera_lvds
set_instance_parameter_value alt_serdes_in {MODE} {RX_DPA-FIFO}
@ -233,7 +139,7 @@ proc p_alt_serdes {} {
set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked
}
if {$m_mode == "OUT"} {
if {($m_mode == "OUT") && ($m_device_family == "Arria 10")} {
add_instance alt_serdes_out altera_lvds
set_instance_parameter_value alt_serdes_out {MODE} {TX}
@ -256,4 +162,49 @@ proc p_alt_serdes {} {
add_interface data_s conduit end
set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in
}
## cyclone v, serdes clock, data-in and data-out
if {($m_mode == "CLK") && ($m_device_family == "Cyclone V")} {
add_instance alt_serdes_pll altera_pll
set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3}
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
add_interface rst reset sink
set_interface_property rst EXPORT_OF alt_serdes_pll.reset
add_interface ref_clk clock sink
set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
add_interface locked conduit end
set_interface_property locked EXPORT_OF alt_serdes_pll.locked
add_interface hs_clk clock source
set_interface_property hs_clk EXPORT_OF alt_serdes_pll.outclk0
add_interface loaden clock source
set_interface_property loaden EXPORT_OF alt_serdes_pll.outclk1
add_interface ls_clk clock source
set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
add_instance alt_serdes_pll_reconfig altera_pll_reconfig
add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
add_interface drp_clk clock sink
set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
add_interface drp_rst reset sink
set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
add_interface pll_reconfig avalon slave
set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
}
}

119
library/altera/common/ad_serdes_clk.v
View File

@ -35,21 +35,30 @@
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8)
// do NOT use this module AS IT IS, the sub modules must be generated inside _hw.tcl file.
// replace __*__ names with the component names
`timescale 1ps/1ps
module ad_serdes_clk #(
module __ad_serdes_clk__ #(
// parameters
parameter DEVICE_TYPE = 0 ) (
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 1,
parameter SERDES_FACTOR = 8,
parameter MMCM_OR_BUFR_N = 1,
parameter MMCM_CLKIN_PERIOD = 1.667,
parameter MMCM_VCO_DIV = 6,
parameter MMCM_VCO_MUL = 12.000,
parameter MMCM_CLK0_DIV = 2.000,
parameter MMCM_CLK1_DIV = 6) (
// clock and divided clock
input rst,
input clk_in_p,
input clk_in_n,
output clk,
output div_clk,
output out_clk,
@ -70,7 +79,8 @@ module ad_serdes_clk #(
// local parameter
localparam C5SOC = 1;
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal registers
@ -85,12 +95,13 @@ module ad_serdes_clk #(
reg up_drp_locked_int = 'd0;
// internal signals
wire up_drp_reset;
wire [31:0] up_drp_rdata_int_s;
wire up_drp_busy_int_s;
wire up_drp_locked_int_s;
wire buf_loaden;
wire buf_lvdsclk;
wire loaden_s;
wire clk_s;
// defaults
@ -145,52 +156,58 @@ module ad_serdes_clk #(
end
generate
if (DEVICE_TYPE == C5SOC) begin
alt_serdes_clk_core i_core (
.rst_reset (rst),
.ref_clk_clk (clk_in_p),
.locked_export (up_drp_locked_int_s),
.hs_phase_phout (phase),
.hs_clk_clk (buf_lvdsclk),
.loaden_clk (buf_loaden),
.ls_clk_clk (div_clk),
.drp_clk_clk (up_clk),
.drp_rst_reset (up_drp_reset),
.pll_reconfig_waitrequest (up_drp_busy_int_s),
.pll_reconfig_read (up_drp_rd_int),
.pll_reconfig_write (up_drp_wr_int),
.pll_reconfig_readdata (up_drp_rdata_int_s),
.pll_reconfig_address (up_drp_addr_int),
.pll_reconfig_writedata (up_drp_wdata_int));
// clock buffer
cyclonev_pll_lvds_output #(
.pll_loaden_enable_disable("true"),
.pll_lvdsclk_enable_disable("true"))
cyclonev_pll_lvds_output_inst (
.ccout({buf_loaden, buf_lvdsclk}),
.loaden(loaden),
.lvdsclk(clk));
end else begin
alt_serdes_clk_core i_core (
.rst_reset (rst),
.ref_clk_clk (clk_in_p),
.locked_export (up_drp_locked_int_s),
.hs_phase_phout (phase),
.hs_clk_lvds_clk (clk),
.loaden_loaden (loaden),
.ls_clk_clk (div_clk),
.drp_clk_clk (up_clk),
.drp_rst_reset (up_drp_reset),
.pll_reconfig_waitrequest (up_drp_busy_int_s),
.pll_reconfig_read (up_drp_rd_int),
.pll_reconfig_write (up_drp_wr_int),
.pll_reconfig_readdata (up_drp_rdata_int_s),
.pll_reconfig_address (up_drp_addr_int),
.pll_reconfig_writedata (up_drp_wdata_int));
end
if (DEVICE_TYPE == ARRIA10) begin
__alt_serdes_clk_core__ i_core (
.rst_reset (rst),
.ref_clk_clk (clk_in_p),
.locked_export (up_drp_locked_int_s),
.hs_phase_phout (phase),
.hs_clk_lvds_clk (clk),
.loaden_loaden (loaden),
.ls_clk_clk (div_clk),
.drp_clk_clk (up_clk),
.drp_rst_reset (up_drp_reset),
.pll_reconfig_waitrequest (up_drp_busy_int_s),
.pll_reconfig_read (up_drp_rd_int),
.pll_reconfig_write (up_drp_wr_int),
.pll_reconfig_readdata (up_drp_rdata_int_s),
.pll_reconfig_address (up_drp_addr_int),
.pll_reconfig_writedata (up_drp_wdata_int));
end
endgenerate
generate
if (DEVICE_TYPE == CYCLONE5) begin
assign phase = 8'd0;
__alt_serdes_clk_core__ i_core (
.rst_reset (rst),
.ref_clk_clk (clk_in_p),
.locked_export (up_drp_locked_int_s),
.hs_clk_clk (clk_s),
.loaden_clk (loaden_s),
.ls_clk_clk (div_clk),
.drp_clk_clk (up_clk),
.drp_rst_reset (up_drp_reset),
.pll_reconfig_waitrequest (up_drp_busy_int_s),
.pll_reconfig_read (up_drp_rd_int),
.pll_reconfig_write (up_drp_wr_int),
.pll_reconfig_readdata (up_drp_rdata_int_s),
.pll_reconfig_address (up_drp_addr_int),
.pll_reconfig_writedata (up_drp_wdata_int));
cyclonev_pll_lvds_output #(
.pll_loaden_enable_disable ("true"),
.pll_lvdsclk_enable_disable ("true"))
i_clk_buf (
.ccout ({loaden_s, clk_s}),
.loaden (loaden),
.lvdsclk (clk));
end
endgenerate
endmodule
// ***************************************************************************