axi_fmcadc5_sync- updates
Rejeesh Kutty
parent
c248d5ac6a
commit
81570ada75
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@ -34,62 +34,40 @@
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// this module is a helper core for linux. as much as possible, try not to use this core.
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// best thing to do is look at no-os and implement a proper frame work in linux.
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// most controls are scattered around other cores, here we collect them to provide a common access.
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`timescale 1ns/100ps
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module axi_gpreg #(
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module axi_fmcadc5_sync (
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parameter integer ID = 0,
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parameter integer NUM_OF_IO = 8,
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parameter integer NUM_OF_CLK_MONS = 8,
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parameter integer BUF_ENABLE_0 = 1,
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parameter integer BUF_ENABLE_1 = 1,
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parameter integer BUF_ENABLE_2 = 1,
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parameter integer BUF_ENABLE_3 = 1,
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parameter integer BUF_ENABLE_4 = 1,
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parameter integer BUF_ENABLE_5 = 1,
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parameter integer BUF_ENABLE_6 = 1,
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parameter integer BUF_ENABLE_7 = 1)
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// receive interface
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input rx_clk,
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output rx_sysref,
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input rx_sync_0,
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input rx_sync_1,
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output rx_sysref_p,
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output rx_sysref_n,
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output rx_sync_0_p,
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output rx_sync_0_n,
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output rx_sync_1_p,
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output rx_sync_1_n,
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(
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// delay interface
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input delay_rst,
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input delay_clk,
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// io
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// spi override
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output [ 31:0] up_gp_ioenb_0,
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output [ 31:0] up_gp_out_0,
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input [ 31:0] up_gp_in_0,
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output [ 31:0] up_gp_ioenb_1,
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output [ 31:0] up_gp_out_1,
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input [ 31:0] up_gp_in_1,
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output [ 31:0] up_gp_ioenb_2,
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output [ 31:0] up_gp_out_2,
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input [ 31:0] up_gp_in_2,
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output [ 31:0] up_gp_ioenb_3,
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output [ 31:0] up_gp_out_3,
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input [ 31:0] up_gp_in_3,
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output [ 31:0] up_gp_ioenb_4,
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output [ 31:0] up_gp_out_4,
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input [ 31:0] up_gp_in_4,
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output [ 31:0] up_gp_ioenb_5,
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output [ 31:0] up_gp_out_5,
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input [ 31:0] up_gp_in_5,
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output [ 31:0] up_gp_ioenb_6,
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output [ 31:0] up_gp_out_6,
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input [ 31:0] up_gp_in_6,
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output [ 31:0] up_gp_ioenb_7,
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output [ 31:0] up_gp_out_7,
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input [ 31:0] up_gp_in_7,
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// clock monitors
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input d_clk_0,
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input d_clk_1,
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input d_clk_2,
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input d_clk_3,
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input d_clk_4,
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input d_clk_5,
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input d_clk_6,
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input d_clk_7,
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output up_spi_req,
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input up_spi_gnt,
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output [ 7:0] up_spi_csn,
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output up_spi_clk,
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output up_spi_mosi,
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input up_spi_miso,
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// axi interface
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@ -115,122 +93,264 @@ module axi_gpreg #(
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot);
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// version
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localparam [31:0] PCORE_VERSION = 32'h00040063;
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localparam integer BUF_ENABLE[7:0] = {BUF_ENABLE_7, BUF_ENABLE_6, BUF_ENABLE_5, BUF_ENABLE_4,
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BUF_ENABLE_3, BUF_ENABLE_2, BUF_ENABLE_1, BUF_ENABLE_0};
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// internal registers
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reg up_wack_d = 'd0;
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reg up_rack_d = 'd0;
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reg [ 31:0] up_rdata_d = 'd0;
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reg up_wack = 'd0;
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reg up_sysref_ack_t_m1 = 'd0;
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reg up_sysref_ack_t_m2 = 'd0;
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reg up_sysref_ack_t_m3 = 'd0;
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reg up_sysref_control_t = 'd0;
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reg [ 1:0] up_sysref_mode_e = 'd0;
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reg up_sysref_mode_i = 'd0;
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reg up_sysref_req_t = 'd0;
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reg up_sysref_status = 'd0;
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reg up_sync_control_t = 'd0;
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reg up_sync_mode = 'd0;
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reg up_sync_disable_1 = 'd0;
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reg up_sync_disable_0 = 'd0;
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reg up_sync_status_t_m1 = 'd0;
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reg up_sync_status_t_m2 = 'd0;
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reg up_sync_status_t_m3 = 'd0;
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reg up_sync_status_1 = 'd0;
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reg up_sync_status_0 = 'd0;
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reg up_delay_ld = 'd0;
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reg [ 4:0] up_delay_wdata = 'd0;
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reg up_spi_req_int = 'd0;
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reg [ 7:0] up_spi_csn_int = 'd0;
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reg [ 5:0] up_spi_cnt = 'd0;
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reg [ 31:0] up_spi_clk_32 = 'd0;
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reg [ 31:0] up_spi_out_32 = 'd0;
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reg [ 31:0] up_spi_in_32 = 'd0;
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reg [ 7:0] up_spi_out = 'd0;
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reg [ 31:0] up_scratch = 'd0;
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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reg [ 31:0] up_rdata = 'd0;
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reg [ 7:0] rx_sysref_cnt = 'd0;
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reg rx_sysref_control_t_m1 = 'd0;
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reg rx_sysref_control_t_m2 = 'd0;
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reg rx_sysref_control_t_m3 = 'd0;
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reg [ 1:0] rx_sysref_mode_e = 'd0;
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reg rx_sysref_mode_i = 'd0;
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reg rx_sysref_req_t_m1 = 'd0;
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reg rx_sysref_req_t_m2 = 'd0;
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reg rx_sysref_req_t_m3 = 'd0;
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reg rx_sysref_req = 'd0;
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reg rx_sysref_e = 'd0;
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reg rx_sysref_i = 'd0;
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reg rx_sysref_ack_t = 'd0;
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reg rx_sysref_enb_e = 'd0;
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reg rx_sysref_enb_i = 'd0;
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reg rx_sync_control_t_m1 = 'd0;
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reg rx_sync_control_t_m2 = 'd0;
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reg rx_sync_control_t_m3 = 'd0;
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reg rx_sync_mode = 'd0;
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reg rx_sync_disable_1 = 'd0;
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reg rx_sync_disable_0 = 'd0;
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reg rx_sync_out_1 = 'd0;
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reg rx_sync_out_0 = 'd0;
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reg [ 7:0] rx_sync_cnt = 'd0;
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reg rx_sync_hold_1 = 'd0;
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reg rx_sync_hold_0 = 'd0;
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reg rx_sync_status_t = 'd0;
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reg rx_sync_status_1 = 'd0;
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reg rx_sync_status_0 = 'd0;
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// internal signals
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wire up_sysref_ack_t_s;
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wire up_sync_status_t_s;
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wire [ 31:0] up_spi_out_32_s;
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wire [ 7:0] up_spi_in_s;
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wire rx_sysref_control_t_s;
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wire rx_sysref_req_t_s;
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wire rx_sysref_enb_e_s;
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wire rx_sync_control_t_s;
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wire up_delay_locked_s;
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wire up_wreq_s;
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wire [ 13:0] up_waddr_s;
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wire [ 31:0] up_wdata_s;
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wire up_rreq_s;
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wire [ 13:0] up_raddr_s;
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wire up_rstn;
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wire up_clk;
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wire up_wreq;
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wire [ 13:0] up_waddr;
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wire [ 31:0] up_wdata;
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wire up_rreq;
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wire [ 13:0] up_raddr;
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wire up_wreq_s;
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wire up_rreq_s;
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wire [ 31:0] up_gp_ioenb_s[7:0];
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wire [ 31:0] up_gp_out_s[7:0];
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wire [ 31:0] up_gp_in_s[7:0];
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wire [ 7:0] d_clk_s;
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wire [ 16:0] up_wack_s;
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wire [ 16:0] up_rack_s;
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wire [ 31:0] up_rdata_s[16:0];
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// signal name changes
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assign up_rstn = s_axi_aresetn;
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assign up_clk = s_axi_aclk;
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// split-up interfaces
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// sysref register(s)
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assign up_gp_ioenb_0 = up_gp_ioenb_s[0];
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assign up_gp_out_0 = up_gp_out_s[0];
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assign up_gp_in_s[0] = up_gp_in_0;
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assign up_gp_ioenb_1 = up_gp_ioenb_s[1];
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assign up_gp_out_1 = up_gp_out_s[1];
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assign up_gp_in_s[1] = up_gp_in_1;
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assign up_gp_ioenb_2 = up_gp_ioenb_s[2];
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assign up_gp_out_2 = up_gp_out_s[2];
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assign up_gp_in_s[2] = up_gp_in_2;
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assign up_gp_ioenb_3 = up_gp_ioenb_s[3];
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assign up_gp_out_3 = up_gp_out_s[3];
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assign up_gp_in_s[3] = up_gp_in_3;
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assign up_gp_ioenb_4 = up_gp_ioenb_s[4];
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assign up_gp_out_4 = up_gp_out_s[4];
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assign up_gp_in_s[4] = up_gp_in_4;
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assign up_gp_ioenb_5 = up_gp_ioenb_s[5];
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assign up_gp_out_5 = up_gp_out_s[5];
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assign up_gp_in_s[5] = up_gp_in_5;
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assign up_gp_ioenb_6 = up_gp_ioenb_s[6];
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assign up_gp_out_6 = up_gp_out_s[6];
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assign up_gp_in_s[6] = up_gp_in_6;
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assign up_gp_ioenb_7 = up_gp_ioenb_s[7];
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assign up_gp_out_7 = up_gp_out_s[7];
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assign up_gp_in_s[7] = up_gp_in_7;
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assign up_sysref_ack_t_s = up_sysref_ack_t_m3 ^ up_sysref_ack_t_m2;
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assign d_clk_s[0] = d_clk_0;
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assign d_clk_s[1] = d_clk_1;
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assign d_clk_s[2] = d_clk_2;
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assign d_clk_s[3] = d_clk_3;
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assign d_clk_s[4] = d_clk_4;
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assign d_clk_s[5] = d_clk_5;
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assign d_clk_s[6] = d_clk_6;
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assign d_clk_s[7] = d_clk_7;
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// up signals
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always @(posedge up_clk or negedge up_rstn) begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_wack_d <= 1'd0;
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up_rack_d <= 1'd0;
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up_rdata_d <= 32'd0;
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up_sysref_ack_t_m1 <= 1'd0;
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up_sysref_ack_t_m2 <= 1'd0;
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up_sysref_ack_t_m3 <= 1'd0;
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end else begin
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up_wack_d <= | up_wack_s;
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up_rack_d <= | up_rack_s;
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up_rdata_d <= up_rdata_s[ 0] | up_rdata_s[ 1] | up_rdata_s[ 2] |
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up_rdata_s[ 3] | up_rdata_s[ 4] | up_rdata_s[ 5] | up_rdata_s[ 6] |
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up_rdata_s[ 7] | up_rdata_s[ 8] | up_rdata_s[ 9] | up_rdata_s[10] |
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up_rdata_s[11] | up_rdata_s[12] | up_rdata_s[13] | up_rdata_s[14] |
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up_rdata_s[15] | up_rdata_s[16];
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up_sysref_ack_t_m1 <= rx_sysref_ack_t;
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up_sysref_ack_t_m2 <= up_sysref_ack_t_m1;
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up_sysref_ack_t_m3 <= up_sysref_ack_t_m2;
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end
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end
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// generic register map
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_sysref_control_t <= 1'd0;
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up_sysref_mode_e <= 2'd0;
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up_sysref_mode_i <= 1'd0;
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up_sysref_req_t <= 1'd0;
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up_sysref_status <= 1'b0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0040)) begin
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up_sysref_control_t <= ~up_sysref_control_t;
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up_sysref_mode_e <= up_wdata_s[5:4];
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up_sysref_mode_i <= up_wdata_s[0];
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end
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if (up_sysref_status == 1'b1) begin
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if (up_sysref_ack_t_s == 1'b1) begin
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up_sysref_req_t <= up_sysref_req_t;
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up_sysref_status <= 1'b0;
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end
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end else if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0041)) begin
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if (up_wdata_s[0] == 1'b1) begin
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up_sysref_req_t <= ~up_sysref_req_t;
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up_sysref_status <= 1'b1;
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end
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end
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end
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end
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assign up_wack_s[16] = up_wack;
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assign up_rack_s[16] = up_rack;
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assign up_rdata_s[16] = up_rdata;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
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// processor write interface
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// sync register(s)
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_sync_control_t <= 1'd0;
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up_sync_mode <= 1'd0;
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up_sync_disable_1 <= 1'd0;
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up_sync_disable_0 <= 1'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0030)) begin
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up_sync_control_t <= ~up_sync_control_t;
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up_sync_mode <= up_wdata_s[2];
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up_sync_disable_1 <= up_wdata_s[1];
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up_sync_disable_0 <= up_wdata_s[0];
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end
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end
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end
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// simple current status (no persistence)
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assign up_sync_status_t_s = up_sync_status_t_m3 ^ up_sync_status_t_m2;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_sync_status_t_m1 <= 1'd0;
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up_sync_status_t_m2 <= 1'd0;
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up_sync_status_t_m3 <= 1'd0;
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up_sync_status_1 <= 1'd0;
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up_sync_status_0 <= 1'd0;
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end else begin
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up_sync_status_t_m1 <= rx_sync_status_t;
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up_sync_status_t_m2 <= up_sync_status_t_m1;
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up_sync_status_t_m3 <= up_sync_status_t_m2;
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if (up_sync_status_t_s == 1'b1) begin
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up_sync_status_1 <= rx_sync_status_1;
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up_sync_status_0 <= rx_sync_status_0;
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end
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end
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end
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// delay register(s)
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_delay_ld <= 1'd0;
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up_delay_wdata <= 5'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0020)) begin
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up_delay_ld <= 1'b1;
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end else begin
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up_delay_ld <= 1'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0020)) begin
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up_delay_wdata <= up_wdata_s[4:0];
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end
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end
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end
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// spi access
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assign up_spi_req = up_spi_req_int;
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assign up_spi_csn = up_spi_csn_int;
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assign up_spi_clk = up_spi_clk_32[31];
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assign up_spi_mosi = up_spi_out_32[31];
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assign up_spi_out_32_s[31:28] = {4{up_wdata_s[7]}};
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assign up_spi_out_32_s[27:24] = {4{up_wdata_s[6]}};
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assign up_spi_out_32_s[23:20] = {4{up_wdata_s[5]}};
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assign up_spi_out_32_s[19:16] = {4{up_wdata_s[4]}};
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assign up_spi_out_32_s[15:12] = {4{up_wdata_s[3]}};
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assign up_spi_out_32_s[11: 8] = {4{up_wdata_s[2]}};
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assign up_spi_out_32_s[ 7: 4] = {4{up_wdata_s[1]}};
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assign up_spi_out_32_s[ 3: 0] = {4{up_wdata_s[0]}};
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assign up_spi_in_s[7] = up_spi_in_32[28];
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assign up_spi_in_s[6] = up_spi_in_32[24];
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assign up_spi_in_s[5] = up_spi_in_32[20];
|
||||
assign up_spi_in_s[4] = up_spi_in_32[16];
|
||||
assign up_spi_in_s[3] = up_spi_in_32[12];
|
||||
assign up_spi_in_s[2] = up_spi_in_32[ 8];
|
||||
assign up_spi_in_s[1] = up_spi_in_32[ 4];
|
||||
assign up_spi_in_s[0] = up_spi_in_32[ 0];
|
||||
|
||||
// spi register(s)
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_spi_req_int <= 1'd0;
|
||||
up_spi_csn_int <= {8{1'b1}};
|
||||
up_spi_cnt <= 6'd0;
|
||||
up_spi_clk_32 <= 32'd0;
|
||||
up_spi_out_32 <= 32'd0;
|
||||
up_spi_in_32 <= 32'd0;
|
||||
up_spi_out <= 8'd0;
|
||||
end else begin
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0010)) begin
|
||||
up_spi_req_int <= up_wdata_s[0];
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0012)) begin
|
||||
up_spi_csn_int <= up_wdata_s[7:0];
|
||||
end
|
||||
if (up_spi_cnt[5] == 1'b1) begin
|
||||
up_spi_cnt <= up_spi_cnt + 1'b1;
|
||||
up_spi_clk_32 <= {up_spi_clk_32[30:0], 1'd0};
|
||||
up_spi_out_32 <= {up_spi_out_32[30:0], 1'd0};
|
||||
up_spi_in_32 <= {up_spi_in_32[30:0], up_spi_miso};
|
||||
up_spi_out <= up_spi_out;
|
||||
end else if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0013)) begin
|
||||
up_spi_cnt <= 6'h20;
|
||||
up_spi_clk_32 <= {8{4'h6}};
|
||||
up_spi_out_32 <= up_spi_out_32_s;
|
||||
up_spi_in_32 <= {31'd0, up_spi_miso};
|
||||
up_spi_out <= up_wdata_s[7:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// scratch register(s)
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wack <= 'd0;
|
||||
up_scratch <= 'd0;
|
||||
end else begin
|
||||
up_wack <= up_wreq_s;
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
|
||||
up_scratch <= up_wdata;
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0002)) begin
|
||||
up_scratch <= up_wdata_s;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -239,15 +359,30 @@ module axi_gpreg #(
|
|||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wack <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
end else begin
|
||||
up_wack <= up_wreq_s;
|
||||
up_rack <= up_rreq_s;
|
||||
if (up_rreq_s == 1'b1) begin
|
||||
case (up_raddr[7:0])
|
||||
8'h00: up_rdata <= PCORE_VERSION;
|
||||
8'h01: up_rdata <= ID;
|
||||
8'h02: up_rdata <= up_scratch;
|
||||
case (up_raddr_s)
|
||||
14'h0000: up_rdata <= PCORE_VERSION;
|
||||
14'h0001: up_rdata <= ID;
|
||||
14'h0002: up_rdata <= up_scratch;
|
||||
14'h0010: up_rdata <= {31'd0, up_spi_req_int};
|
||||
14'h0011: up_rdata <= {31'd0, up_spi_gnt};
|
||||
14'h0012: up_rdata <= {24'd0, up_spi_csn_int};
|
||||
14'h0013: up_rdata <= {24'd0, up_spi_out};
|
||||
14'h0014: up_rdata <= {24'd0, up_spi_in_s};
|
||||
14'h0015: up_rdata <= {31'd0, up_spi_cnt[5]};
|
||||
14'h0020: up_rdata <= {27'd0, up_delay_wdata};
|
||||
14'h0021: up_rdata <= {27'd0, up_delay_rdata};
|
||||
14'h0022: up_rdata <= {31'd0, up_delay_locked_s};
|
||||
14'h0030: up_rdata <= {29'd0, up_sync_mode, up_sync_disable_1, up_sync_disable_0};
|
||||
14'h0031: up_rdata <= {30'd0, up_sync_status_1, up_sync_status_0};
|
||||
14'h0040: up_rdata <= {26'd0, up_sysref_mode_e, 3'b0, up_sysref_mode_i};
|
||||
14'h0041: up_rdata <= {31'd0, up_sysref_status};
|
||||
default: up_rdata <= 0;
|
||||
endcase
|
||||
end else begin
|
||||
|
|
@ -256,70 +391,121 @@ module axi_gpreg #(
|
|||
end
|
||||
end
|
||||
|
||||
// instantiations
|
||||
// sysref-control at receive clock
|
||||
|
||||
genvar n;
|
||||
generate
|
||||
|
||||
// gpio
|
||||
|
||||
if (NUM_OF_IO < 8) begin
|
||||
for (n = NUM_OF_IO; n < 8; n = n + 1) begin: g_unused_io
|
||||
assign up_gp_ioenb_s[n] = 32'd0;
|
||||
assign up_gp_out_s[n] = 32'd0;
|
||||
assign up_wack_s[n] = 1'd0;
|
||||
assign up_rdata_s[n] = 32'd0;
|
||||
assign up_rack_s[n] = 1'd0;
|
||||
end
|
||||
always @(posedge rx_clk) begin
|
||||
rx_sysref_cnt <= rx_sysref_cnt + 1'b1;
|
||||
end
|
||||
|
||||
for (n = 0; n < NUM_OF_IO; n = n + 1) begin: g_io
|
||||
axi_gpreg_io #(.ID (16+n)) i_gpreg_io (
|
||||
.up_gp_ioenb (up_gp_ioenb_s[n]),
|
||||
.up_gp_out (up_gp_out_s[n]),
|
||||
.up_gp_in (up_gp_in_s[n]),
|
||||
.up_rstn (up_rstn),
|
||||
assign rx_sysref_control_t_s = rx_sysref_control_t_m3 ^ rx_sysref_control_t_m2;
|
||||
assign rx_sysref_req_t_s = rx_sysref_req_t_m3 ^ rx_sysref_req_t_m2;
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
rx_sysref_control_t_m1 <= up_sysref_control_t;
|
||||
rx_sysref_control_t_m2 <= rx_sysref_control_t_m1;
|
||||
rx_sysref_control_t_m3 <= rx_sysref_control_t_m2;
|
||||
if (rx_sysref_control_t_s == 1'b1) begin
|
||||
rx_sysref_mode_e <= up_sysref_mode_e;
|
||||
rx_sysref_mode_i <= up_sysref_mode_i;
|
||||
end
|
||||
rx_sysref_req_t_m1 <= up_sysref_req_t;
|
||||
rx_sysref_req_t_m2 <= rx_sysref_req_t_m1;
|
||||
rx_sysref_req_t_m3 <= rx_sysref_req_t_m2;
|
||||
if ((rx_sysref_cnt == 8'd0) || (rx_sysref_req_t_s == 1'b1)) begin
|
||||
rx_sysref_req <= rx_sysref_req_t_s;
|
||||
end
|
||||
end
|
||||
|
||||
assign rx_sysref_enb_e_s = (rx_sysref_mode_e == 2'b10) ? rx_sysref_req :
|
||||
((rx_sysref_mode_e == 2'b00) ? 1'b1 : 1'b0);
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
rx_sysref_e <= rx_sysref_cnt[7] & rx_sysref_enb_e;
|
||||
rx_sysref_i <= rx_sysref_cnt[7] & rx_sysref_enb_i;
|
||||
if (rx_sysref_cnt == 8'd0) begin
|
||||
if (rx_sysref_enb_e == 1'b1) begin
|
||||
rx_sysref_ack_t <= ~rx_sysref_ack_t;
|
||||
end
|
||||
rx_sysref_enb_e <= rx_sysref_enb_e_s;
|
||||
rx_sysref_enb_i <= ~rx_sysref_mode_i;
|
||||
end
|
||||
end
|
||||
|
||||
// sync-control at receive clock
|
||||
|
||||
assign rx_sync_control_t_s = rx_sync_control_t_m3 ^ rx_sync_control_t_m2;
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
rx_sync_control_t_m1 <= up_sync_control_t;
|
||||
rx_sync_control_t_m2 <= rx_sync_control_t_m1;
|
||||
rx_sync_control_t_m3 <= rx_sync_control_t_m2;
|
||||
if (rx_sync_control_t_s == 1'b1) begin
|
||||
rx_sync_mode <= up_sync_mode;
|
||||
rx_sync_disable_1 <= up_sync_disable_1;
|
||||
rx_sync_disable_0 <= up_sync_disable_0;
|
||||
end
|
||||
if (rx_sync_mode == 1'b1) begin
|
||||
rx_sync_out_1 <= ~rx_sync_disable_1 & rx_sync_1 & rx_sync_0;
|
||||
rx_sync_out_0 <= ~rx_sync_disable_0 & rx_sync_1 & rx_sync_0;
|
||||
end else begin
|
||||
rx_sync_out_1 <= ~rx_sync_disable_1 & rx_sync_1;
|
||||
rx_sync_out_0 <= ~rx_sync_disable_0 & rx_sync_0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
rx_sync_cnt <= rx_sync_cnt + 1'b1;
|
||||
if ((rx_sync_cnt == 8'd0) || (rx_sync_1 == 1'b0)) begin
|
||||
rx_sync_hold_1 <= rx_sync_1;
|
||||
end
|
||||
if ((rx_sync_cnt == 8'd0) || (rx_sync_0 == 1'b0)) begin
|
||||
rx_sync_hold_0 <= rx_sync_0;
|
||||
end
|
||||
if (rx_sync_cnt == 8'd0) begin
|
||||
rx_sync_status_t <= ~rx_sync_status_t;
|
||||
rx_sync_status_1 <= rx_sync_hold_1;
|
||||
rx_sync_status_0 <= rx_sync_hold_0;
|
||||
end
|
||||
end
|
||||
|
||||
// sync buffers
|
||||
|
||||
OBUFDS i_obufds_rx_sync_1 (
|
||||
.I (rx_sync_out_1),
|
||||
.O (rx_sync_1_p),
|
||||
.OB (rx_sync_1_n));
|
||||
|
||||
OBUFDS i_obufds_rx_sync_0 (
|
||||
.I (rx_sync_out_0),
|
||||
.O (rx_sync_0_p),
|
||||
.OB (rx_sync_0_n));
|
||||
|
||||
// sysref delay control
|
||||
|
||||
assign rx_sysref = rx_sysref_i;
|
||||
|
||||
ad_lvds_out #(
|
||||
.DEVICE_TYPE (0),
|
||||
.SINGLE_ENDED (0),
|
||||
.IODELAY_ENABLE (1),
|
||||
.IODELAY_CTRL (1),
|
||||
.IODELAY_GROUP ("FMCADC5_SYSREF_IODELAY_GROUP"))
|
||||
i_rx_sysref (
|
||||
.tx_clk (rx_clk),
|
||||
.tx_data_p (rx_sysref_e),
|
||||
.tx_data_n (rx_sysref_e),
|
||||
.tx_data_out_p (rx_sysref_p),
|
||||
.tx_data_out_n (rx_sysref_n),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[n]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[n]),
|
||||
.up_rack (up_rack_s[n]));
|
||||
end
|
||||
|
||||
// clock monitors
|
||||
|
||||
if (NUM_OF_CLK_MONS < 8) begin
|
||||
for (n = NUM_OF_CLK_MONS; n < 8; n = n + 1) begin: g_unused_clock_mon
|
||||
assign up_wack_s[(8+n)] = 1'd0;
|
||||
assign up_rdata_s[(8+n)] = 32'd0;
|
||||
assign up_rack_s[(8+n)] = 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
for (n = 0; n < NUM_OF_CLK_MONS; n = n + 1) begin: g_clock_mon
|
||||
axi_gpreg_clock_mon #(
|
||||
.ID (32+n),
|
||||
.BUF_ENABLE (BUF_ENABLE[n]))
|
||||
i_gpreg_clock_mon (
|
||||
.d_clk (d_clk_s[n]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[(8+n)]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[(8+n)]),
|
||||
.up_rack (up_rack_s[(8+n)]));
|
||||
end
|
||||
|
||||
endgenerate
|
||||
.up_dld (up_delay_ld),
|
||||
.up_dwdata (up_delay_wdata),
|
||||
.up_drdata (up_delay_rdata),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (up_delay_locked_s));
|
||||
|
||||
// up == micro("u") processor
|
||||
|
||||
up_axi i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
|
|
@ -340,14 +526,14 @@ module axi_gpreg #(
|
|||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_d),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_d),
|
||||
.up_rack (up_rack_d));
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,27 @@
|
|||
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sysref_ack_t_m1* && IS_SEQUENTIAL}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sync_status_t_m1* && IS_SEQUENTIAL}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sync_status_1* && IS_SEQUENTIAL}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sync_status_0* && IS_SEQUENTIAL}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sysref_control_t_m1* && IS_SEQUENTIAL}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sysref_mode_e* && IS_SEQUENTIAL}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sysref_mode_i* && IS_SEQUENTIAL}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sysref_req_t_m1* && IS_SEQUENTIAL}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sync_control_t_m1* && IS_SEQUENTIAL}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sync_mode* && IS_SEQUENTIAL}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sync_disable_1* && IS_SEQUENTIAL}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sync_disable_0* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *d_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_count_toggle_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *d_count_hold* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_d_count* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *up_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_count_toggle_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *up_d_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *up_sysref_ack_t_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *up_sync_status_t_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *up_sync_status_1* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *up_sync_status_0* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_control_t_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_mode_e* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_mode_i* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_req_t_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_control_t_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_mode* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_1* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_0* && IS_SEQUENTIAL}]
|
||||
|
||||
|
|
|
|||
|
|
@ -3,53 +3,12 @@
|
|||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip.tcl
|
||||
|
||||
adi_ip_create axi_gpreg
|
||||
adi_ip_files axi_gpreg [list \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
adi_ip_create axi_fmcadc5_sync
|
||||
adi_ip_files axi_fmcadc5_sync [list \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"axi_gpreg_constr.xdc" \
|
||||
"axi_gpreg_io.v" \
|
||||
"axi_gpreg_clock_mon.v" \
|
||||
"axi_gpreg.v" ]
|
||||
|
||||
adi_ip_properties axi_gpreg
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 0} \
|
||||
[ipx::get_ports up_gp_*_0 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 1} \
|
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[ipx::get_ports up_gp_*_1 -of_objects [ipx::current_core]]
|
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 2} \
|
||||
[ipx::get_ports up_gp_*_2 -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 3} \
|
||||
[ipx::get_ports up_gp_*_3 -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 4} \
|
||||
[ipx::get_ports up_gp_*_4 -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 5} \
|
||||
[ipx::get_ports up_gp_*_5 -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 6} \
|
||||
[ipx::get_ports up_gp_*_6 -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 7} \
|
||||
[ipx::get_ports up_gp_*_7 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 0} \
|
||||
[ipx::get_ports d_clk_0 -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 1} \
|
||||
[ipx::get_ports d_clk_1 -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 2} \
|
||||
[ipx::get_ports d_clk_2 -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 3} \
|
||||
[ipx::get_ports d_clk_3 -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 4} \
|
||||
[ipx::get_ports d_clk_4 -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 5} \
|
||||
[ipx::get_ports d_clk_5 -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 6} \
|
||||
[ipx::get_ports d_clk_6 -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 7} \
|
||||
[ipx::get_ports d_clk_7 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
|
||||
"axi_fmcadc5_sync_constr.xdc" \
|
||||
"axi_fmcadc5_sync.v" ]
|
||||
|
||||
adi_ip_properties axi_fmcadc5_sync
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue