axi_fifo2s: include bus width/clock transfer
Rejeesh Kutty
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888ab888d2
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81b4cd532d
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_fifo2s_adc (
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// fifo interface
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adc_rst,
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adc_clk,
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adc_wr,
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adc_wdata,
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adc_wovf,
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adc_dwr,
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adc_ddata,
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// axi interface
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axi_drst,
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axi_clk,
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axi_xfer_status);
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// parameters
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parameter ADC_DATA_WIDTH = 128;
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parameter AXI_DATA_WIDTH = 512;
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localparam ADC_MEM_RATIO = AXI_DATA_WIDTH/ADC_DATA_WIDTH;
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// adc interface
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input adc_rst;
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input adc_clk;
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input adc_wr;
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input [ADC_DATA_WIDTH-1:0] adc_wdata;
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output adc_wovf;
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output adc_dwr;
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output [AXI_DATA_WIDTH-1:0] adc_ddata;
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// axi interface
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input axi_clk;
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input axi_drst;
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input [ 3:0] axi_xfer_status;
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// internal registers
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reg adc_wovf = 'd0;
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reg [ 2:0] adc_wcnt_int = 'd0;
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reg adc_dwr = 'd0;
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reg [AXI_DATA_WIDTH-1:0] adc_ddata = 'd0;
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// internal signals
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wire [ 3:0] adc_xfer_status_s;
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// write interface: supports only 64, 128, 256 and 512 against 512
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always @(posedge adc_clk) begin
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if (adc_rst == 1'b1) begin
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adc_wovf <= 'd0;
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adc_wcnt_int <= 'd0;
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adc_dwr <= 'd0;
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adc_ddata <= 'd0;
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end else begin
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adc_wovf <= | adc_xfer_status_s;
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adc_wcnt_int <= adc_wcnt_int + 1'b1;
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case (ADC_MEM_RATIO)
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8: begin
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adc_dwr <= adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] & adc_wcnt_int[2];
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adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*7)] <= adc_wdata;
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adc_ddata[((ADC_DATA_WIDTH*7)-1):(ADC_DATA_WIDTH*0)] <=
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adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*1)];
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end
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4: begin
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adc_dwr <= adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1];
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adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*3)] <= adc_wdata;
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adc_ddata[((ADC_DATA_WIDTH*3)-1):(ADC_DATA_WIDTH*0)] <=
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adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*1)];
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end
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2: begin
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adc_dwr <= adc_wr & adc_wcnt_int[0];
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adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)] <= adc_wdata;
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adc_ddata[((ADC_DATA_WIDTH*1)-1):(ADC_DATA_WIDTH*0)] <=
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adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)];
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end
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1: begin
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adc_dwr <= adc_wr;
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adc_ddata <= adc_wdata;
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end
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default: begin
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adc_dwr <= 'd0;
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adc_ddata <= 'd0;
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end
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endcase
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end
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end
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// instantiations
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up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
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.up_rstn (~adc_rst),
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.up_clk (adc_clk),
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.up_data_status (adc_xfer_status_s),
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.d_rst (axi_drst),
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.d_clk (axi_clk),
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.d_data_status (axi_xfer_status));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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