From 8289262807243c76ccca6c5ead48851e07686bd6 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 16 Apr 2015 10:50:10 +0200 Subject: [PATCH] axi_spdif_tx: CDC overhaul Use common prefix for CDC elements and add the proper constraints to the XDC file. And add a missing stage to the toggle synchronizers. Also drop a some unnecessary resets. Signed-off-by: Lars-Peter Clausen --- library/axi_spdif_tx/axi_spdif_tx_constr.xdc | 11 ++++++-- library/axi_spdif_tx/tx_encoder.vhd | 28 +++++++++++--------- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/library/axi_spdif_tx/axi_spdif_tx_constr.xdc b/library/axi_spdif_tx/axi_spdif_tx_constr.xdc index fd40910d9..7cb959144 100644 --- a/library/axi_spdif_tx/axi_spdif_tx_constr.xdc +++ b/library/axi_spdif_tx/axi_spdif_tx_constr.xdc @@ -1,4 +1,11 @@ +set_property ASYNC_REG TRUE \ + [get_cells -hier cdc_sync_stage1_*_reg] \ + [get_cells -hier cdc_sync_stage2_*_reg] +set_false_path \ + -from [get_cells -hier cdc_sync_stage0_*_reg -filter {PRIMITIVE_SUBGROUP == flop}] \ + -to [get_cells -hier cdc_sync_stage1_*_reg -filter {PRIMITIVE_SUBGROUP == flop}] - - +set_false_path \ + -from [get_cells -hier spdif_out_reg -filter {PRIMITIVE_SUBGROUP == flop}] \ + -to [get_cells -hier spdif_tx_o_reg -filter {PRIMITIVE_SUBGROUP == flop}] diff --git a/library/axi_spdif_tx/tx_encoder.vhd b/library/axi_spdif_tx/tx_encoder.vhd index caf270beb..7310697dc 100644 --- a/library/axi_spdif_tx/tx_encoder.vhd +++ b/library/axi_spdif_tx/tx_encoder.vhd @@ -92,9 +92,11 @@ architecture rtl of tx_encoder is signal par_vector : std_logic_vector(26 downto 0); signal send_audio : std_logic; + signal cdc_sync_stage0_tick_counter : std_logic := '0'; + signal cdc_sync_stage1_tick_counter : std_logic := '0'; + signal cdc_sync_stage2_tick_counter : std_logic := '0'; + signal cdc_sync_stage3_tick_counter : std_logic := '0'; signal tick_counter : std_logic; - signal tick_counter_d1 : std_logic; - signal tick_counter_d2 : std_logic; constant X_PREAMBLE : std_logic_vector(0 to 7) := "11100010"; constant Y_PREAMBLE : std_logic_vector(0 to 7) := "11100100"; @@ -149,24 +151,30 @@ begin DCLK : process (data_clk) begin if rising_edge(data_clk) then - tick_counter <= not tick_counter; + cdc_sync_stage0_tick_counter <= not cdc_sync_stage0_tick_counter; end if; end process DCLK; + process (up_clk) begin + if rising_edge(up_clk) then + cdc_sync_stage1_tick_counter <= cdc_sync_stage0_tick_counter; + cdc_sync_stage2_tick_counter <= cdc_sync_stage1_tick_counter; + cdc_sync_stage3_tick_counter <= cdc_sync_stage2_tick_counter; + end if; + end process; + + tick_counter <= cdc_sync_stage3_tick_counter xor cdc_sync_stage2_tick_counter; + CGEN: process (up_clk) begin if rising_edge(up_clk) then if resetn = '0' or conf_txen = '0' then clk_cnt <= 0; - tick_counter_d1 <= '0'; - tick_counter_d2 <= '0'; spdif_clk_en <= '0'; else - tick_counter_d1 <= tick_counter; - tick_counter_d2 <= tick_counter_d1; spdif_clk_en <= '0'; - if (tick_counter_d1 xor tick_counter_d2) = '1' then + if tick_counter = '1' then if clk_cnt < to_integer(unsigned(conf_ratio)) then clk_cnt <= clk_cnt + 1; else @@ -221,11 +229,7 @@ begin TXSYNC: process (data_clk) begin if (rising_edge(data_clk)) then - if resetn = '0' then - spdif_tx_o <= '0'; - else spdif_tx_o <= spdif_out; - end if; end if; end process TXSYNC;