diff --git a/projects/common/a10soc/a10soc_system_assign.tcl b/projects/common/a10soc/a10soc_system_assign.tcl
new file mode 100755
index 000000000..145c90666
--- /dev/null
+++ b/projects/common/a10soc/a10soc_system_assign.tcl
@@ -0,0 +1,240 @@
+
+# device settings
+
+set_global_assignment -name FAMILY "Arria 10"
+set_global_assignment -name DEVICE 10AX115S3F45E2SGE3
+
+# clocks and resets
+
+set_location_assignment PIN_AR36  -to sys_clk
+set_location_assignment PIN_AR37  -to "sys_clk(n)"
+set_location_assignment PIN_BD27  -to sys_resetn
+set_instance_assignment -name IO_STANDARD LVDS -to sys_clk
+set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_resetn
+
+# ddr3
+
+set_location_assignment PIN_F34   -to ddr3_ref_clk
+set_location_assignment PIN_F35   -to "ddr3_ref_clk(n)"
+
+set_instance_assignment -name IO_STANDARD LVDS -to ddr3_ref_clk
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to ddr3_ref_clk -disable
+
+set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_a[14]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_a[13]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_a[12]
+
+set_location_assignment PIN_R30   -to ddr3_clk_p      ; ## 1.5 V   V1  MEM_CLK_P          
+set_location_assignment PIN_R31   -to ddr3_clk_n      ; ## 1.5 V   V2  MEM_CLK_N          
+set_location_assignment PIN_M32   -to ddr3_a[0]       ; ## 1.5 V   F1  MEM_ADDR_CMD0      
+set_location_assignment PIN_L32   -to ddr3_a[1]       ; ## 1.5 V   H1  MEM_ADDR_CMD1      
+set_location_assignment PIN_N34   -to ddr3_a[2]       ; ## 1.5 V   F2  MEM_ADDR_CMD2      
+set_location_assignment PIN_M35   -to ddr3_a[3]       ; ## 1.5 V   G2  MEM_ADDR_CMD3      
+set_location_assignment PIN_L34   -to ddr3_a[4]       ; ## 1.5 V   H2  MEM_ADDR_CMD4      
+set_location_assignment PIN_K34   -to ddr3_a[5]       ; ## 1.5 V   J2  MEM_ADDR_CMD5      
+set_location_assignment PIN_M33   -to ddr3_a[6]       ; ## 1.5 V   K2  MEM_ADDR_CMD6      
+set_location_assignment PIN_L33   -to ddr3_a[7]       ; ## 1.5 V   G3  MEM_ADDR_CMD7      
+set_location_assignment PIN_J33   -to ddr3_a[8]       ; ## 1.5 V   J3  MEM_ADDR_CMD8      
+set_location_assignment PIN_J32   -to ddr3_a[9]       ; ## 1.5 V   L3  MEM_ADDR_CMD9      
+set_location_assignment PIN_H31   -to ddr3_a[10]      ; ## 1.5 V   E4  MEM_ADDR_CMD10     
+set_location_assignment PIN_J31   -to ddr3_a[11]      ; ## 1.5 V   F4  MEM_ADDR_CMD11     
+set_location_assignment PIN_H34   -to ddr3_a[12]      ; ## 1.5 V   G4  MEM_ADDR_CMD12     
+set_location_assignment PIN_H33   -to ddr3_a[13]      ; ## 1.5 V   H4  MEM_ADDR_CMD13     
+set_location_assignment PIN_G32   -to ddr3_a[14]      ; ## 1.5 V   J4  MEM_ADDR_CMD14     
+set_location_assignment PIN_F33   -to ddr3_ba[0]      ; ## 1.5 V   M1  MEM_ADDR_CMD16     
+set_location_assignment PIN_G35   -to ddr3_ba[1]      ; ## 1.5 V   M2  MEM_ADDR_CMD17     
+set_location_assignment PIN_H35   -to ddr3_ba[2]      ; ## 1.5 V   N2  MEM_ADDR_CMD18     
+set_location_assignment PIN_U33   -to ddr3_cke        ; ## 1.5 V   P5  MEM_ADDR_CMD20     
+set_location_assignment PIN_R34   -to ddr3_cs_n       ; ## 1.5 V   P1  MEM_ADDR_CMD22     
+set_location_assignment PIN_N33   -to ddr3_odt        ; ## 1.5 V   M4  MEM_ADDR_CMD24     
+set_location_assignment PIN_T35   -to ddr3_reset_n    ; ## 1.5 V   K1  MEM_ADDR_CMD27     
+set_location_assignment PIN_T34   -to ddr3_we_n       ; ## 1.5 V   P2  MEM_ADDR_CMD28     
+set_location_assignment PIN_F32   -to ddr3_ras_n      ; ## 1.5 V   L2  MEM_ADDR_CMD26     
+set_location_assignment PIN_G33   -to ddr3_cas_n      ; ## 1.5 V   L4  MEM_ADDR_CMD19     
+set_location_assignment PIN_B26   -to ddr3_dqs_p[0]   ; ## 1.5 V   A6  MEM_DQSA_P0        
+set_location_assignment PIN_C26   -to ddr3_dqs_n[0]   ; ## 1.5 V   A7  MEM_DQSA_N0        
+set_location_assignment PIN_H28   -to ddr3_dqs_p[1]   ; ## 1.5 V   A2  MEM_DQSA_P1        
+set_location_assignment PIN_J27   -to ddr3_dqs_n[1]   ; ## 1.5 V   A3  MEM_DQSA_N1        
+set_location_assignment PIN_C30   -to ddr3_dqs_p[2]   ; ## 1.5 V   A14 MEM_DQSA_P2        
+set_location_assignment PIN_C29   -to ddr3_dqs_n[2]   ; ## 1.5 V   A15 MEM_DQSA_N2        
+set_location_assignment PIN_L30   -to ddr3_dqs_p[3]   ; ## 1.5 V   F18 MEM_DQSA_P3        
+set_location_assignment PIN_L29   -to ddr3_dqs_n[3]   ; ## 1.5 V   G18 MEM_DQSA_N3        
+set_location_assignment PIN_Y32   -to ddr3_dqs_p[4]   ; ## 1.5 V   H18 MEM_DQSB_P0        
+set_location_assignment PIN_AA32  -to ddr3_dqs_n[4]   ; ## 1.5 V   J18 MEM_DQSB_N0        
+set_location_assignment PIN_AJ32  -to ddr3_dqs_p[5]   ; ## 1.5 V   U18 MEM_DQSB_P1        
+set_location_assignment PIN_AJ31  -to ddr3_dqs_n[5]   ; ## 1.5 V   V18 MEM_DQSB_N1        
+set_location_assignment PIN_AA34  -to ddr3_dqs_p[6]   ; ## 1.5 V   V16 MEM_DQSB_P2        
+set_location_assignment PIN_AA33  -to ddr3_dqs_n[6]   ; ## 1.5 V   V17 MEM_DQSB_N2        
+set_location_assignment PIN_AF33  -to ddr3_dqs_p[7]   ; ## 1.5 V   V8  MEM_DQSB_P3        
+set_location_assignment PIN_AF34  -to ddr3_dqs_n[7]   ; ## 1.5 V   V9  MEM_DQSB_N3        
+set_location_assignment PIN_B28   -to ddr3_dq[0]      ; ## 1.5 V   A4  MEM_DQA0           
+set_location_assignment PIN_A28   -to ddr3_dq[1]      ; ## 1.5 V   B4  MEM_DQA1           
+set_location_assignment PIN_A27   -to ddr3_dq[2]      ; ## 1.5 V   B5  MEM_DQA2           
+set_location_assignment PIN_B27   -to ddr3_dq[3]      ; ## 1.5 V   B6  MEM_DQA3           
+set_location_assignment PIN_D27   -to ddr3_dq[4]      ; ## 1.5 V   A8  MEM_DQA4           
+set_location_assignment PIN_E27   -to ddr3_dq[5]      ; ## 1.5 V   B8  MEM_DQA5           
+set_location_assignment PIN_D26   -to ddr3_dq[6]      ; ## 1.5 V   B9  MEM_DQA6           
+set_location_assignment PIN_D28   -to ddr3_dq[7]      ; ## 1.5 V   A10 MEM_DQA7           
+set_location_assignment PIN_G25   -to ddr3_dq[8]      ; ## 1.5 V   B1  MEM_DQA8           
+set_location_assignment PIN_H25   -to ddr3_dq[9]      ; ## 1.5 V   B2  MEM_DQA9           
+set_location_assignment PIN_G26   -to ddr3_dq[10]     ; ## 1.5 V   C2  MEM_DQA10          
+set_location_assignment PIN_H26   -to ddr3_dq[11]     ; ## 1.5 V   C3  MEM_DQA11          
+set_location_assignment PIN_G28   -to ddr3_dq[12]     ; ## 1.5 V   E3  MEM_DQA12          
+set_location_assignment PIN_F27   -to ddr3_dq[13]     ; ## 1.5 V   D4  MEM_DQA13          
+set_location_assignment PIN_K27   -to ddr3_dq[14]     ; ## 1.5 V   D1  MEM_DQA14          
+set_location_assignment PIN_F28   -to ddr3_dq[15]     ; ## 1.5 V   D2  MEM_DQA15          
+set_location_assignment PIN_D31   -to ddr3_dq[16]     ; ## 1.5 V   A12 MEM_DQA16          
+set_location_assignment PIN_E31   -to ddr3_dq[17]     ; ## 1.5 V   B12 MEM_DQA17          
+set_location_assignment PIN_B31   -to ddr3_dq[18]     ; ## 1.5 V   B13 MEM_DQA18          
+set_location_assignment PIN_C31   -to ddr3_dq[19]     ; ## 1.5 V   B14 MEM_DQA19          
+set_location_assignment PIN_A30   -to ddr3_dq[20]     ; ## 1.5 V   C15 MEM_DQA20          
+set_location_assignment PIN_E30   -to ddr3_dq[21]     ; ## 1.5 V   A16 MEM_DQA21          
+set_location_assignment PIN_B30   -to ddr3_dq[22]     ; ## 1.5 V   B16 MEM_DQA22          
+set_location_assignment PIN_D29   -to ddr3_dq[23]     ; ## 1.5 V   A18 MEM_DQA23          
+set_location_assignment PIN_K30   -to ddr3_dq[24]     ; ## 1.5 V   C16 MEM_DQA24          
+set_location_assignment PIN_H30   -to ddr3_dq[25]     ; ## 1.5 V   D16 MEM_DQA25          
+set_location_assignment PIN_G30   -to ddr3_dq[26]     ; ## 1.5 V   E16 MEM_DQA26          
+set_location_assignment PIN_K31   -to ddr3_dq[27]     ; ## 1.5 V   F16 MEM_DQA27          
+set_location_assignment PIN_H29   -to ddr3_dq[28]     ; ## 1.5 V   D17 MEM_DQA28          
+set_location_assignment PIN_K29   -to ddr3_dq[29]     ; ## 1.5 V   C18 MEM_DQA29          
+set_location_assignment PIN_J29   -to ddr3_dq[30]     ; ## 1.5 V   D18 MEM_DQA30          
+set_location_assignment PIN_F29   -to ddr3_dq[31]     ; ## 1.5 V   E18 MEM_DQA31          
+set_location_assignment PIN_AC31  -to ddr3_dq[32]     ; ## 1.5 V   H16 MEM_DQB0           
+set_location_assignment PIN_AB31  -to ddr3_dq[33]     ; ## 1.5 V   J16 MEM_DQB1           
+set_location_assignment PIN_W31   -to ddr3_dq[34]     ; ## 1.5 V   K16 MEM_DQB2           
+set_location_assignment PIN_Y31   -to ddr3_dq[35]     ; ## 1.5 V   L16 MEM_DQB3           
+set_location_assignment PIN_AD31  -to ddr3_dq[36]     ; ## 1.5 V   H17 MEM_DQB4           
+set_location_assignment PIN_AD32  -to ddr3_dq[37]     ; ## 1.5 V   K17 MEM_DQB5           
+set_location_assignment PIN_AD33  -to ddr3_dq[38]     ; ## 1.5 V   K18 MEM_DQB6           
+set_location_assignment PIN_AA30  -to ddr3_dq[39]     ; ## 1.5 V   L18 MEM_DQB7           
+set_location_assignment PIN_AE31  -to ddr3_dq[40]     ; ## 1.5 V   M17 MEM_DQB8           
+set_location_assignment PIN_AE32  -to ddr3_dq[41]     ; ## 1.5 V   N18 MEM_DQB9           
+set_location_assignment PIN_AE30  -to ddr3_dq[42]     ; ## 1.5 V   P17 MEM_DQB10          
+set_location_assignment PIN_AF30  -to ddr3_dq[43]     ; ## 1.5 V   P18 MEM_DQB11          
+set_location_assignment PIN_AG33  -to ddr3_dq[44]     ; ## 1.5 V   R18 MEM_DQB12          
+set_location_assignment PIN_AG32  -to ddr3_dq[45]     ; ## 1.5 V   T16 MEM_DQB13          
+set_location_assignment PIN_AH33  -to ddr3_dq[46]     ; ## 1.5 V   T17 MEM_DQB14          
+set_location_assignment PIN_AH31  -to ddr3_dq[47]     ; ## 1.5 V   T18 MEM_DQB15          
+set_location_assignment PIN_U31   -to ddr3_dq[48]     ; ## 1.5 V   U15 MEM_DQB16          
+set_location_assignment PIN_W33   -to ddr3_dq[49]     ; ## 1.5 V   T14 MEM_DQB17          
+set_location_assignment PIN_W32   -to ddr3_dq[50]     ; ## 1.5 V   U14 MEM_DQB18          
+set_location_assignment PIN_V31   -to ddr3_dq[51]     ; ## 1.5 V   V14 MEM_DQB19          
+set_location_assignment PIN_Y34   -to ddr3_dq[52]     ; ## 1.5 V   T13 MEM_DQB20          
+set_location_assignment PIN_W35   -to ddr3_dq[53]     ; ## 1.5 V   T12 MEM_DQB21          
+set_location_assignment PIN_W34   -to ddr3_dq[54]     ; ## 1.5 V   U12 MEM_DQB22          
+set_location_assignment PIN_V34   -to ddr3_dq[55]     ; ## 1.5 V   V12 MEM_DQB23          
+set_location_assignment PIN_AH35  -to ddr3_dq[56]     ; ## 1.5 V   T10 MEM_DQB24          
+set_location_assignment PIN_AJ34  -to ddr3_dq[57]     ; ## 1.5 V   U10 MEM_DQB25          
+set_location_assignment PIN_AJ33  -to ddr3_dq[58]     ; ## 1.5 V   V10 MEM_DQB26          
+set_location_assignment PIN_AH34  -to ddr3_dq[59]     ; ## 1.5 V   T9  MEM_DQB27          
+set_location_assignment PIN_AD35  -to ddr3_dq[60]     ; ## 1.5 V   T8  MEM_DQB28          
+set_location_assignment PIN_AE34  -to ddr3_dq[61]     ; ## 1.5 V   U8  MEM_DQB29          
+set_location_assignment PIN_AC33  -to ddr3_dq[62]     ; ## 1.5 V   U7  MEM_DQB30          
+set_location_assignment PIN_AD34  -to ddr3_dq[63]     ; ## 1.5 V   V6  MEM_DQB31          
+set_location_assignment PIN_E26   -to ddr3_dm[0]      ; ## 1.5 V   B10 MEM_DMA0           
+set_location_assignment PIN_G27   -to ddr3_dm[1]      ; ## 1.5 V   C4  MEM_DMA1           
+set_location_assignment PIN_A29   -to ddr3_dm[2]      ; ## 1.5 V   B17 MEM_DMA2           
+set_location_assignment PIN_F30   -to ddr3_dm[3]      ; ## 1.5 V   F17 MEM_DMA3           
+set_location_assignment PIN_AB32  -to ddr3_dm[4]      ; ## 1.5 V   M16 MEM_DMB0           
+set_location_assignment PIN_AG31  -to ddr3_dm[5]      ; ## 1.5 V   U16 MEM_DMB1           
+set_location_assignment PIN_Y35   -to ddr3_dm[6]      ; ## 1.5 V   U11 MEM_DMB2           
+set_location_assignment PIN_AC34  -to ddr3_dm[7]      ; ## 1.5 V   U6  MEM_DMB3           
+set_location_assignment PIN_J34   -to ddr3_rzq        ; ## RZQ
+
+# ethernet interface
+
+set_location_assignment PIN_BD24 -to eth_ref_clk
+set_location_assignment PIN_BC24 -to "eth_ref_clk(n)"
+set_location_assignment PIN_AV24 -to eth_rxd
+set_location_assignment PIN_AW24 -to "eth_rxd(n)"
+set_location_assignment PIN_BC23 -to eth_txd
+set_location_assignment PIN_BD23 -to "eth_txd(n)"
+
+set_instance_assignment -name IO_STANDARD LVDS -to eth_ref_clk
+set_instance_assignment -name IO_STANDARD LVDS -to eth_rxd
+set_instance_assignment -name IO_STANDARD LVDS -to eth_txd
+
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_ref_clk -disable
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_rxd -disable
+
+set_location_assignment PIN_AW23 -to eth_resetn
+set_location_assignment PIN_AF13 -to eth_mdc
+set_location_assignment PIN_AL18 -to eth_mdio
+set_location_assignment PIN_AG13 -to eth_intn
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_resetn
+set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_mdc
+set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_mdio
+set_instance_assignment -name IO_STANDARD "1.8 V" -to eth_intn
+
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to eth_ref_clk
+
+# leds
+
+set_location_assignment PIN_L28   -to gpio_bd_o[0]  ; ## led-g0-d10
+set_location_assignment PIN_K26   -to gpio_bd_o[1]  ; ## led-g1-d9
+set_location_assignment PIN_K25   -to gpio_bd_o[2]  ; ## led-g2-d8
+set_location_assignment PIN_L25   -to gpio_bd_o[3]  ; ## led-g3-d7
+set_location_assignment PIN_J24   -to gpio_bd_o[4]  ; ## led-g4-d6
+set_location_assignment PIN_A19   -to gpio_bd_o[5]  ; ## led-g5-d5
+set_location_assignment PIN_C18   -to gpio_bd_o[6]  ; ## led-g6-d4
+set_location_assignment PIN_D18   -to gpio_bd_o[7]  ; ## led-g7-d3
+set_location_assignment PIN_L27   -to gpio_bd_o[8]  ; ## led-r0-d10  
+set_location_assignment PIN_J26   -to gpio_bd_o[9]  ; ## led-r1-d9   
+set_location_assignment PIN_K24   -to gpio_bd_o[10] ; ## led-r2-d8
+set_location_assignment PIN_L23   -to gpio_bd_o[11] ; ## led-r3-d7
+set_location_assignment PIN_B20   -to gpio_bd_o[12] ; ## led-r4-d6
+set_location_assignment PIN_C19   -to gpio_bd_o[13] ; ## led-r5-d5
+set_location_assignment PIN_D19   -to gpio_bd_o[14] ; ## led-r6-d4
+set_location_assignment PIN_M23   -to gpio_bd_o[15] ; ## led-r7-d3
+set_location_assignment PIN_A24   -to gpio_bd_i[0]  ; ## dipsw0
+set_location_assignment PIN_B23   -to gpio_bd_i[1]  ; ## dipsw1
+set_location_assignment PIN_A23   -to gpio_bd_i[2]  ; ## dipsw2
+set_location_assignment PIN_B22   -to gpio_bd_i[3]  ; ## dipsw3
+set_location_assignment PIN_A22   -to gpio_bd_i[4]  ; ## dipsw4
+set_location_assignment PIN_B21   -to gpio_bd_i[5]  ; ## dipsw5
+set_location_assignment PIN_C21   -to gpio_bd_i[6]  ; ## dipsw6
+set_location_assignment PIN_A20   -to gpio_bd_i[7]  ; ## dipsw7
+set_location_assignment PIN_T12   -to gpio_bd_i[8]  ; ## pb0-s3
+set_location_assignment PIN_U12   -to gpio_bd_i[9]  ; ## pb1-s2
+set_location_assignment PIN_U11   -to gpio_bd_i[10] ; ## pb2-s1
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[0] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[1] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[2] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[3] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[4] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[5] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[6] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[7] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[8] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[9] 
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[10]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[11]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[12]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[13]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[14]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[15]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[8]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[9]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[10]
+
+# globals
+
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+
+
diff --git a/projects/common/a10soc/a10soc_system_bd.qsys b/projects/common/a10soc/a10soc_system_bd.qsys
new file mode 100644
index 000000000..7bdd08068
--- /dev/null
+++ b/projects/common/a10soc/a10soc_system_bd.qsys
@@ -0,0 +1,2801 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element a10gx_system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element mem_clk
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element mem_rst
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element sys_cpu
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_cpu.debug_mem_slave
+   {
+      datum baseAddress
+      {
+         value = "270010368";
+         type = "String";
+      }
+   }
+   element sys_cpu_interconnect
+   {
+      datum _sortIndex
+      {
+         value = "20";
+         type = "int";
+      }
+   }
+   element sys_cpu_interconnect.s0
+   {
+      datum baseAddress
+      {
+         value = "268435456";
+         type = "String";
+      }
+   }
+   element sys_ddr3_cntrl
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element sys_ethernet
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element sys_ethernet.control_port
+   {
+      datum baseAddress
+      {
+         value = "270012416";
+         type = "String";
+      }
+   }
+   element sys_ethernet_dma_rx
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element sys_ethernet_dma_rx.csr
+   {
+      datum baseAddress
+      {
+         value = "270013600";
+         type = "String";
+      }
+   }
+   element sys_ethernet_dma_rx.descriptor_slave
+   {
+      datum baseAddress
+      {
+         value = "270013504";
+         type = "String";
+      }
+   }
+   element sys_ethernet_dma_rx.response
+   {
+      datum baseAddress
+      {
+         value = "270013664";
+         type = "String";
+      }
+   }
+   element sys_ethernet_dma_tx
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element sys_ethernet_dma_tx.csr
+   {
+      datum baseAddress
+      {
+         value = "270013568";
+         type = "String";
+      }
+   }
+   element sys_ethernet_dma_tx.descriptor_slave
+   {
+      datum baseAddress
+      {
+         value = "270013536";
+         type = "String";
+      }
+   }
+   element sys_ethernet_reset
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
+   element sys_gpio_bd
+   {
+      datum _sortIndex
+      {
+         value = "16";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_gpio_bd.s1
+   {
+      datum baseAddress
+      {
+         value = "270013648";
+         type = "String";
+      }
+   }
+   element sys_gpio_in
+   {
+      datum _sortIndex
+      {
+         value = "17";
+         type = "int";
+      }
+   }
+   element sys_gpio_in.s1
+   {
+      datum baseAddress
+      {
+         value = "270013632";
+         type = "String";
+      }
+   }
+   element sys_gpio_out
+   {
+      datum _sortIndex
+      {
+         value = "18";
+         type = "int";
+      }
+   }
+   element sys_gpio_out.s1
+   {
+      datum baseAddress
+      {
+         value = "270013696";
+         type = "String";
+      }
+   }
+   element sys_id
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_id.control_slave
+   {
+      datum baseAddress
+      {
+         value = "270013672";
+         type = "String";
+      }
+   }
+   element sys_int_mem
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_int_mem.s1
+   {
+      datum _lockedAddress
+      {
+         value = "0";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "269746176";
+         type = "String";
+      }
+   }
+   element sys_irq
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+   }
+   element sys_mem_interconnect
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+   }
+   element sys_rst
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element sys_spi
+   {
+      datum _sortIndex
+      {
+         value = "19";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_spi.spi_control_port
+   {
+      datum baseAddress
+      {
+         value = "270013440";
+         type = "String";
+      }
+   }
+   element sys_timer
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_timer.s1
+   {
+      datum baseAddress
+      {
+         value = "270013472";
+         type = "String";
+      }
+   }
+   element sys_timer_2nd
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element sys_timer_2nd.s1
+   {
+      datum baseAddress
+      {
+         value = "270013728";
+         type = "String";
+      }
+   }
+   element sys_tlb_mem
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element sys_tlb_mem.s1
+   {
+      datum baseAddress
+      {
+         value = "270532608";
+         type = "String";
+      }
+   }
+   element sys_tlb_mem.s2
+   {
+      datum baseAddress
+      {
+         value = "270532608";
+         type = "String";
+      }
+   }
+   element sys_uart
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_uart.avalon_jtag_slave
+   {
+      datum baseAddress
+      {
+         value = "270013680";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="10AX115S3F45E2SGE3" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="mem_clk" internal="mem_clk.out_clk" type="clock" dir="start" />
+ <interface name="mem_rst" internal="mem_rst.out_reset" type="reset" dir="start" />
+ <interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
+ <interface
+   name="sys_cpu_m_avl"
+   internal="sys_cpu_interconnect.m0"
+   type="avalon"
+   dir="start" />
+ <interface
+   name="sys_ddr3_cntrl_mem"
+   internal="sys_ddr3_cntrl.mem"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ddr3_cntrl_mem_conduit_end"
+   internal="sys_ddr3_cntrl.mem_conduit_end" />
+ <interface
+   name="sys_ddr3_cntrl_oct"
+   internal="sys_ddr3_cntrl.oct"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ddr3_cntrl_oct_conduit_end"
+   internal="sys_ddr3_cntrl.oct_conduit_end" />
+ <interface
+   name="sys_ddr3_cntrl_pll_ref_clk"
+   internal="sys_ddr3_cntrl.pll_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_ddr3_cntrl_ref_clk"
+   internal="sys_ddr3_cntrl.pll_ref_clk_clock_sink" />
+ <interface
+   name="sys_ddr3_cntrl_status_conduit_end"
+   internal="sys_ddr3_cntrl.status_conduit_end" />
+ <interface
+   name="sys_ethernet_mdio"
+   internal="sys_ethernet.mac_mdio_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_ref_clk"
+   internal="sys_ethernet.pcs_ref_clk_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_ethernet_reset"
+   internal="sys_ethernet_reset.out_reset"
+   type="reset"
+   dir="start" />
+ <interface
+   name="sys_ethernet_rgmii"
+   internal="sys_ethernet.mac_rgmii_connection" />
+ <interface
+   name="sys_ethernet_rx_clk"
+   internal="sys_ethernet.pcs_mac_rx_clock_connection" />
+ <interface
+   name="sys_ethernet_sgmii"
+   internal="sys_ethernet.serial_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_status"
+   internal="sys_ethernet.mac_status_connection" />
+ <interface
+   name="sys_ethernet_tx_clk"
+   internal="sys_ethernet.pcs_mac_tx_clock_connection" />
+ <interface
+   name="sys_gpio_bd"
+   internal="sys_gpio_bd.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_gpio_in"
+   internal="sys_gpio_in.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_gpio_out"
+   internal="sys_gpio_out.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_intr"
+   internal="sys_irq.receiver_irq"
+   type="interrupt"
+   dir="start" />
+ <interface
+   name="sys_mem_s_avl"
+   internal="sys_mem_interconnect.s0"
+   type="avalon"
+   dir="end" />
+ <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
+ <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
+ <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="133333250" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="133333250" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module name="sys_cpu" kind="altera_nios2_gen2" version="15.1" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
+  <parameter name="cdx_enabled" value="false" />
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="cpuArchRev" value="1" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
+  <parameter name="dataAddrWidth" value="29" />
+  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="dataMasterHighPerformanceMapParam" value="" />
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' type='altera_emif_arch_nf.ctrl_amm_0' /><slave name='sys_cpu_interconnect.s0' start='0x10000000' end='0x10100000' type='altera_avalon_mm_bridge.s0' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_ethernet.control_port' start='0x10181000' end='0x10181400' type='altera_eth_tse.control_port' /><slave name='sys_spi.spi_control_port' start='0x10181400' end='0x10181420' type='altera_avalon_spi.spi_control_port' /><slave name='sys_timer.s1' start='0x10181420' end='0x10181440' type='altera_avalon_timer.s1' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x10181440' end='0x10181460' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x10181460' end='0x10181480' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.csr' start='0x10181480' end='0x101814A0' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_rx.csr' start='0x101814A0' end='0x101814C0' type='altera_msgdma.csr' /><slave name='sys_gpio_in.s1' start='0x101814C0' end='0x101814D0' type='altera_avalon_pio.s1' /><slave name='sys_gpio_bd.s1' start='0x101814D0' end='0x101814E0' type='altera_avalon_pio.s1' /><slave name='sys_ethernet_dma_rx.response' start='0x101814E0' end='0x101814E8' type='altera_msgdma.response' /><slave name='sys_id.control_slave' start='0x101814E8' end='0x101814F0' type='altera_avalon_sysid_qsys.control_slave' /><slave name='sys_uart.avalon_jtag_slave' start='0x101814F0' end='0x101814F8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sys_gpio_out.s1' start='0x10181500' end='0x10181510' type='altera_avalon_pio.s1' /><slave name='sys_timer_2nd.s1' start='0x10181520' end='0x10181540' type='altera_avalon_timer.s1' /></address-map>]]></parameter>
+  <parameter name="data_master_high_performance_paddr_base" value="0" />
+  <parameter name="data_master_high_performance_paddr_size" value="0" />
+  <parameter name="data_master_paddr_base" value="0" />
+  <parameter name="data_master_paddr_size" value="0" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="dcache_numTCDM" value="1" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_size" value="32768" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="debug_datatrigger" value="0" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_enabled" value="true" />
+  <parameter name="debug_hwbreakpoint" value="0" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="debug_traceStorage" value="onchip_trace" />
+  <parameter name="debug_traceType" value="none" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="deviceFamilyName" value="Arria 10" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+  <parameter name="dividerType" value="no_div" />
+  <parameter name="exceptionOffset" value="32" />
+  <parameter name="exceptionSlave">sys_ddr3_cntrl_arch.ctrl_amm_0</parameter>
+  <parameter name="faAddrWidth" value="1" />
+  <parameter name="faSlaveMapParam" value="" />
+  <parameter name="fa_cache_line" value="2" />
+  <parameter name="fa_cache_linesize" value="0" />
+  <parameter name="flash_instruction_master_paddr_base" value="0" />
+  <parameter name="flash_instruction_master_paddr_size" value="0" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="icache_numTCIM" value="1" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_size" value="32768" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="impl" value="Fast" />
+  <parameter name="instAddrWidth" value="29" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' type='altera_emif_arch_nf.ctrl_amm_0' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
+  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+  <parameter name="instruction_master_paddr_base" value="0" />
+  <parameter name="instruction_master_paddr_size" value="0" />
+  <parameter name="internalIrqMaskSystemInfo" value="65535" />
+  <parameter name="io_regionbase" value="0" />
+  <parameter name="io_regionsize" value="0" />
+  <parameter name="master_addr_map" value="false" />
+  <parameter name="mmu_TLBMissExcOffset" value="4096" />
+  <parameter name="mmu_TLBMissExcSlave" value="sys_tlb_mem.s2" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="false" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpx_enabled" value="false" />
+  <parameter name="mul_32_impl" value="3" />
+  <parameter name="mul_64_impl" value="0" />
+  <parameter name="mul_shift_choice" value="0" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="ocimem_ramInit" value="false" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="resetSlave">sys_ddr3_cntrl_arch.ctrl_amm_0</parameter>
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="setting_allow_break_inst" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_asic_add_scan_mode_input" value="false" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_asic_third_party_synthesis" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_branchpredictiontype" value="Dynamic" />
+  <parameter name="setting_breakslaveoveride" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_dc_ecc_present" value="false" />
+  <parameter name="setting_disable_tmr_inj" value="false" />
+  <parameter name="setting_disableocitrace" value="false" />
+  <parameter name="setting_dtcm_ecc_present" value="false" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="setting_ecc_sim_test_ports" value="false" />
+  <parameter name="setting_exportHostDebugPort" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_exportdebuginfo" value="false" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="setting_fast_register_read" value="false" />
+  <parameter name="setting_ic_ecc_present" value="true" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="setting_itcm_ecc_present" value="false" />
+  <parameter name="setting_mmu_ecc_present" value="true" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="setting_oci_version" value="1" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_removeRAMinit" value="false" />
+  <parameter name="setting_rf_ecc_present" value="true" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_support31bitdcachebypass" value="false" />
+  <parameter name="setting_usedesignware" value="false" />
+  <parameter name="shift_rot_impl" value="0" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
+  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s1' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s1' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s2' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s2' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+  <parameter name="tmr_enabled" value="false" />
+  <parameter name="tracefilename" value="" />
+  <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module
+   name="sys_cpu_interconnect"
+   kind="altera_avalon_mm_bridge"
+   version="15.1"
+   enabled="1">
+  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
+  <parameter name="ADDRESS_WIDTH" value="20" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="LINEWRAPBURSTS" value="0" />
+  <parameter name="MAX_BURST_SIZE" value="1" />
+  <parameter name="MAX_PENDING_RESPONSES" value="4" />
+  <parameter name="PIPELINE_COMMAND" value="1" />
+  <parameter name="PIPELINE_RESPONSE" value="1" />
+  <parameter name="SYMBOL_WIDTH" value="8" />
+  <parameter name="SYSINFO_ADDR_WIDTH" value="10" />
+  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
+  <parameter name="USE_RESPONSE" value="0" />
+ </module>
+ <module name="sys_ddr3_cntrl" kind="altera_emif" version="15.1" enabled="1">
+  <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+  <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+  <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+  <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
+  <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+  <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
+  <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+  <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+  <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+  <parameter name="BOARD_LPDDR3_MAX_CK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_LPDDR3_MAX_DQS_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+  <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_LPDDR3_USER_CK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_LPDDR3_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_LPDDR3_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_RDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_LPDDR3_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_LPDDR3_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
+  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
+  <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+  <parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
+  <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+  <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+  <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+  <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+  <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
+  <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="3.5" />
+  <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+  <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
+  <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+  <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+  <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+  <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+  <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
+  <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
+  <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
+  <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+  <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+  <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
+  <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
+  <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
+  <parameter name="CTRL_DDR3_ECC_EN" value="false" />
+  <parameter name="CTRL_DDR3_MMR_EN" value="false" />
+  <parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
+  <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTRL_DDR3_STARVE_LIMIT" value="10" />
+  <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
+  <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
+  <parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
+  <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
+  <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
+  <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
+  <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
+  <parameter name="CTRL_DDR4_ECC_EN" value="false" />
+  <parameter name="CTRL_DDR4_MMR_EN" value="false" />
+  <parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
+  <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTRL_DDR4_STARVE_LIMIT" value="10" />
+  <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
+  <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
+  <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_ADDR_ORDER_ENUM">LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+  <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+  <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_REORDER_EN" value="true" />
+  <parameter name="CTRL_LPDDR3_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_STARVE_LIMIT" value="10" />
+  <parameter name="CTRL_LPDDR3_USER_PRIORITY_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_USER_REFRESH_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+  <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
+  <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC" value="0" />
+  <parameter name="CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC" value="0" />
+  <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+  <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
+  <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+  <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+  <parameter name="DIAG_DDR3_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_DDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_DDR3_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_DDR3_CAL_ADDR0" value="0" />
+  <parameter name="DIAG_DDR3_CAL_ADDR1" value="8" />
+  <parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
+  <parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
+  <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
+  <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_DDR4_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_DDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_DDR4_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_DDR4_CAL_ADDR0" value="0" />
+  <parameter name="DIAG_DDR4_CAL_ADDR1" value="8" />
+  <parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
+  <parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
+  <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
+  <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
+  <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="false" />
+  <parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+  <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
+  <parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+  <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
+  <parameter name="DIAG_EXPORT_VJI" value="false" />
+  <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
+  <parameter name="DIAG_EXTRA_CONFIGS" value="" />
+  <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
+  <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+  <parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+  <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
+  <parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
+  <parameter name="DIAG_LPDDR3_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_LPDDR3_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_QDR2_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_QDR4_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
+  <parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_RLD2_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_RLD3_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+  <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_RS232_UART_BAUDRATE" value="57600" />
+  <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
+  <parameter name="DIAG_SOFT_NIOS_CLOCK_FREQUENCY" value="100" />
+  <parameter name="DIAG_SOFT_NIOS_MODE">SOFT_NIOS_MODE_DISABLED</parameter>
+  <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
+  <parameter name="DIAG_TG_AVL_2_NUM_CFG_INTERFACES" value="0" />
+  <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
+  <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="DIAG_USE_RS232_UART" value="false" />
+  <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
+  <parameter name="EX_DESIGN_GUI_DDR3_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_DDR3_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_DDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_DDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_DDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_DDR4_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_DDR4_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_DDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_DDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_DDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter
+     name="EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT"
+     value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_QDR2_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_QDR2_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_QDR2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_QDR2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_QDR2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_QDR4_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_QDR4_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_QDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_QDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_QDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_RLD2_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_RLD2_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_RLD2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_RLD2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_RLD2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_RLD3_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_RLD3_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_RLD3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_RLD3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_RLD3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="INTERNAL_TESTING_MODE" value="false" />
+  <parameter name="IS_ED_SLAVE" value="false" />
+  <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
+  <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
+  <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
+  <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
+  <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
+  <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
+  <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
+  <parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
+  <parameter name="MEM_DDR3_CK_WIDTH" value="1" />
+  <parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
+  <parameter name="MEM_DDR3_DLL_EN" value="true" />
+  <parameter name="MEM_DDR3_DM_EN" value="true" />
+  <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_DDR3_DQ_WIDTH" value="64" />
+  <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_7" />
+  <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
+  <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG" value="0x0" />
+  <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="true" />
+  <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
+  <parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
+  <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0" />
+  <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="12" />
+  <parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
+  <parameter name="MEM_DDR3_RTT_WR_ENUM" value="DDR3_RTT_WR_RZQ_4" />
+  <parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
+  <parameter name="MEM_DDR3_R_ODT0_2X2" value="off,off" />
+  <parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
+  <parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
+  <parameter name="MEM_DDR3_R_ODT1_2X2" value="off,off" />
+  <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
+  <parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
+  <parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
+  <parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
+  <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
+  <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
+  <parameter name="MEM_DDR3_TCL" value="13" />
+  <parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
+  <parameter name="MEM_DDR3_TDH_PS" value="55" />
+  <parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
+  <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
+  <parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
+  <parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
+  <parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
+  <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
+  <parameter name="MEM_DDR3_TDS_PS" value="53" />
+  <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
+  <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
+  <parameter name="MEM_DDR3_TIH_PS" value="95" />
+  <parameter name="MEM_DDR3_TINIT_US" value="500" />
+  <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
+  <parameter name="MEM_DDR3_TIS_PS" value="60" />
+  <parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
+  <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
+  <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
+  <parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
+  <parameter name="MEM_DDR3_TRCD_NS" value="10.285" />
+  <parameter name="MEM_DDR3_TREFI_US" value="7.8" />
+  <parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
+  <parameter name="MEM_DDR3_TRP_NS" value="10.285" />
+  <parameter name="MEM_DDR3_TRRD_CYC" value="6" />
+  <parameter name="MEM_DDR3_TRTP_CYC" value="8" />
+  <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
+  <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
+  <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
+  <parameter name="MEM_DDR3_TWTR_CYC" value="8" />
+  <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
+  <parameter name="MEM_DDR3_WTCL" value="9" />
+  <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
+  <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,off" />
+  <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
+  <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
+  <parameter name="MEM_DDR3_W_ODT1_2X2" value="off,on" />
+  <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
+  <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
+  <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
+  <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
+  <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
+  <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
+  <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
+  <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
+  <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
+  <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_AUTO</parameter>
+  <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
+  <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
+  <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
+  <parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
+  <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
+  <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
+  <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
+  <parameter name="MEM_DDR4_CAL_MODE" value="0" />
+  <parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
+  <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
+  <parameter name="MEM_DDR4_CK_WIDTH" value="1" />
+  <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="true" />
+  <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
+  <parameter name="MEM_DDR4_DLL_EN" value="true" />
+  <parameter name="MEM_DDR4_DM_EN" value="true" />
+  <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
+  <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
+  <parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
+  <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
+  <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
+  <parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
+  <parameter name="MEM_DDR4_LRDIMM_EXTENDED_CONFIG" value="0000000000000000" />
+  <parameter name="MEM_DDR4_LRDIMM_VREFDQ_VALUE" value="1D" />
+  <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
+  <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="true" />
+  <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
+  <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
+  <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
+  <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
+  <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_DDR4_RDIMM_CONFIG">0000000000000000000000000000000F000000</parameter>
+  <parameter name="MEM_DDR4_READ_DBI" value="false" />
+  <parameter name="MEM_DDR4_READ_PREAMBLE" value="2" />
+  <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
+  <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
+  <parameter name="MEM_DDR4_RTT_NOM_ENUM">DDR4_RTT_NOM_ODT_DISABLED</parameter>
+  <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
+  <parameter name="MEM_DDR4_RTT_WR_ENUM" value="DDR4_RTT_WR_RZQ_1" />
+  <parameter name="MEM_DDR4_R_ODT0_1X1" value="off" />
+  <parameter name="MEM_DDR4_R_ODT0_2X2" value="off,off" />
+  <parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
+  <parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
+  <parameter name="MEM_DDR4_R_ODT1_2X2" value="off,off" />
+  <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
+  <parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
+  <parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
+  <parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
+  <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
+  <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2400" />
+  <parameter name="MEM_DDR4_TCCD_L_CYC" value="6" />
+  <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
+  <parameter name="MEM_DDR4_TCL" value="18" />
+  <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
+  <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
+  <parameter name="MEM_DDR4_TDQSCK_PS" value="165" />
+  <parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
+  <parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
+  <parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
+  <parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
+  <parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
+  <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
+  <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
+  <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
+  <parameter name="MEM_DDR4_TFAW_NS" value="21.0" />
+  <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
+  <parameter name="MEM_DDR4_TIH_PS" value="95" />
+  <parameter name="MEM_DDR4_TINIT_US" value="500" />
+  <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
+  <parameter name="MEM_DDR4_TIS_PS" value="60" />
+  <parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
+  <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
+  <parameter name="MEM_DDR4_TQH_UI" value="0.76" />
+  <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
+  <parameter name="MEM_DDR4_TRAS_NS" value="32.0" />
+  <parameter name="MEM_DDR4_TRCD_NS" value="15.0" />
+  <parameter name="MEM_DDR4_TREFI_US" value="7.8" />
+  <parameter name="MEM_DDR4_TRFC_NS" value="260.0" />
+  <parameter name="MEM_DDR4_TRP_NS" value="15.0" />
+  <parameter name="MEM_DDR4_TRRD_L_CYC" value="6" />
+  <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
+  <parameter name="MEM_DDR4_TWLH_PS" value="108.0" />
+  <parameter name="MEM_DDR4_TWLS_PS" value="108.0" />
+  <parameter name="MEM_DDR4_TWR_NS" value="15.0" />
+  <parameter name="MEM_DDR4_TWTR_L_CYC" value="9" />
+  <parameter name="MEM_DDR4_TWTR_S_CYC" value="3" />
+  <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
+  <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="60.0" />
+  <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
+  <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
+  <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
+  <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
+  <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
+  <parameter name="MEM_DDR4_WTCL" value="12" />
+  <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
+  <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,off" />
+  <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
+  <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
+  <parameter name="MEM_DDR4_W_ODT1_2X2" value="off,on" />
+  <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
+  <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
+  <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
+  <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
+  <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_LPDDR3_BANK_ADDR_WIDTH" value="3" />
+  <parameter name="MEM_LPDDR3_BL" value="LPDDR3_BL_BL8" />
+  <parameter name="MEM_LPDDR3_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_LPDDR3_DATA_LATENCY" value="LPDDR3_DL_RL12_WL6" />
+  <parameter name="MEM_LPDDR3_DISCRETE_CS_WIDTH" value="1" />
+  <parameter name="MEM_LPDDR3_DM_EN" value="true" />
+  <parameter name="MEM_LPDDR3_DQODT">LPDDR3_DQODT_DISABLE</parameter>
+  <parameter name="MEM_LPDDR3_DQ_WIDTH" value="32" />
+  <parameter name="MEM_LPDDR3_DRV_STR">LPDDR3_DRV_STR_40D_40U</parameter>
+  <parameter name="MEM_LPDDR3_NWR" value="LPDDR3_NWR_NWR10" />
+  <parameter name="MEM_LPDDR3_PDODT">LPDDR3_PDODT_DISABLED</parameter>
+  <parameter name="MEM_LPDDR3_ROW_ADDR_WIDTH" value="15" />
+  <parameter name="MEM_LPDDR3_R_ODT0_1X1" value="off" />
+  <parameter name="MEM_LPDDR3_R_ODT0_2X2" value="off,off" />
+  <parameter name="MEM_LPDDR3_R_ODT0_4X4" value="off,off,on,on" />
+  <parameter name="MEM_LPDDR3_R_ODT1_2X2" value="off,off" />
+  <parameter name="MEM_LPDDR3_R_ODT1_4X4" value="off,off,off,off" />
+  <parameter name="MEM_LPDDR3_R_ODT2_4X4" value="on,on,off,off" />
+  <parameter name="MEM_LPDDR3_R_ODT3_4X4" value="off,off,off,off" />
+  <parameter name="MEM_LPDDR3_R_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_LPDDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_LPDDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_LPDDR3_SPEEDBIN_ENUM">LPDDR3_SPEEDBIN_1600</parameter>
+  <parameter name="MEM_LPDDR3_TDH_DC_MV" value="100" />
+  <parameter name="MEM_LPDDR3_TDH_PS" value="100" />
+  <parameter name="MEM_LPDDR3_TDQSCK_PS" value="614" />
+  <parameter name="MEM_LPDDR3_TDQSQ_PS" value="135" />
+  <parameter name="MEM_LPDDR3_TDQSS_CYC" value="1.25" />
+  <parameter name="MEM_LPDDR3_TDSH_CYC" value="0.2" />
+  <parameter name="MEM_LPDDR3_TDSS_CYC" value="0.2" />
+  <parameter name="MEM_LPDDR3_TDS_AC_MV" value="150" />
+  <parameter name="MEM_LPDDR3_TDS_PS" value="75" />
+  <parameter name="MEM_LPDDR3_TFAW_NS" value="50.0" />
+  <parameter name="MEM_LPDDR3_TIH_DC_MV" value="100" />
+  <parameter name="MEM_LPDDR3_TIH_PS" value="100" />
+  <parameter name="MEM_LPDDR3_TINIT_US" value="500" />
+  <parameter name="MEM_LPDDR3_TIS_AC_MV" value="150" />
+  <parameter name="MEM_LPDDR3_TIS_PS" value="75" />
+  <parameter name="MEM_LPDDR3_TMRR_CK_CYC" value="4" />
+  <parameter name="MEM_LPDDR3_TMRW_CK_CYC" value="10" />
+  <parameter name="MEM_LPDDR3_TQH_CYC" value="0.38" />
+  <parameter name="MEM_LPDDR3_TQSH_CYC" value="0.38" />
+  <parameter name="MEM_LPDDR3_TRAS_NS" value="42.5" />
+  <parameter name="MEM_LPDDR3_TRCD_NS" value="18.75" />
+  <parameter name="MEM_LPDDR3_TREFI_US" value="3.9" />
+  <parameter name="MEM_LPDDR3_TRFC_NS" value="210.0" />
+  <parameter name="MEM_LPDDR3_TRP_NS" value="18.75" />
+  <parameter name="MEM_LPDDR3_TRRD_CYC" value="2" />
+  <parameter name="MEM_LPDDR3_TRTP_CYC" value="4" />
+  <parameter name="MEM_LPDDR3_TWLH_PS" value="175.0" />
+  <parameter name="MEM_LPDDR3_TWLS_PS" value="175.0" />
+  <parameter name="MEM_LPDDR3_TWR_NS" value="15.0" />
+  <parameter name="MEM_LPDDR3_TWTR_CYC" value="4" />
+  <parameter name="MEM_LPDDR3_USE_DEFAULT_ODT" value="true" />
+  <parameter name="MEM_LPDDR3_W_ODT0_1X1" value="on" />
+  <parameter name="MEM_LPDDR3_W_ODT0_2X2" value="on,off" />
+  <parameter name="MEM_LPDDR3_W_ODT0_4X4" value="on,on,on,on" />
+  <parameter name="MEM_LPDDR3_W_ODT1_2X2" value="off,on" />
+  <parameter name="MEM_LPDDR3_W_ODT1_4X4" value="off,off,off,off" />
+  <parameter name="MEM_LPDDR3_W_ODT2_4X4" value="on,on,on,on" />
+  <parameter name="MEM_LPDDR3_W_ODT3_4X4" value="off,off,off,off" />
+  <parameter name="MEM_LPDDR3_W_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_LPDDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_LPDDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
+  <parameter name="MEM_QDR2_BL" value="4" />
+  <parameter name="MEM_QDR2_BWS_EN" value="true" />
+  <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
+  <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
+  <parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
+  <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
+  <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
+  <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
+  <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
+  <parameter name="MEM_QDR2_THA_NS" value="0.18" />
+  <parameter name="MEM_QDR2_THD_NS" value="0.18" />
+  <parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
+  <parameter name="MEM_QDR2_TSA_NS" value="0.23" />
+  <parameter name="MEM_QDR2_TSD_NS" value="0.23" />
+  <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
+  <parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+  <parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
+  <parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
+  <parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+  <parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
+  <parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+  <parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
+  <parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+  <parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+  <parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
+  <parameter name="MEM_QDR4_TAH_PS" value="125" />
+  <parameter name="MEM_QDR4_TAS_PS" value="125" />
+  <parameter name="MEM_QDR4_TCH_PS" value="150" />
+  <parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
+  <parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
+  <parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
+  <parameter name="MEM_QDR4_TCS_PS" value="150" />
+  <parameter name="MEM_QDR4_TIH_PS" value="125" />
+  <parameter name="MEM_QDR4_TIS_PS" value="125" />
+  <parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
+  <parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
+  <parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
+  <parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
+  <parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
+  <parameter name="MEM_RLD2_BL" value="4" />
+  <parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
+  <parameter name="MEM_RLD2_DM_EN" value="true" />
+  <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
+  <parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
+  <parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
+  <parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
+  <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
+  <parameter name="MEM_RLD2_TAH_NS" value="0.3" />
+  <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
+  <parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
+  <parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
+  <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
+  <parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
+  <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
+  <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
+  <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
+  <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
+  <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
+  <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
+  <parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
+  <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
+  <parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
+  <parameter name="MEM_RLD3_BL" value="2" />
+  <parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
+  <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
+  <parameter name="MEM_RLD3_DM_EN" value="true" />
+  <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
+  <parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
+  <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
+  <parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
+  <parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
+  <parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
+  <parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
+  <parameter name="MEM_RLD3_TDH_DC_MV" value="100" />
+  <parameter name="MEM_RLD3_TDH_PS" value="5" />
+  <parameter name="MEM_RLD3_TDS_AC_MV" value="150" />
+  <parameter name="MEM_RLD3_TDS_PS" value="-30" />
+  <parameter name="MEM_RLD3_TIH_DC_MV" value="100" />
+  <parameter name="MEM_RLD3_TIH_PS" value="65" />
+  <parameter name="MEM_RLD3_TIS_AC_MV" value="150" />
+  <parameter name="MEM_RLD3_TIS_PS" value="85" />
+  <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
+  <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
+  <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
+  <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
+  <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
+  <parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
+  <parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
+  <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
+  <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+  <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_DDR3_DEFAULT_IO" value="false" />
+  <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
+  <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
+  <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="533.333" />
+  <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_15_C1" />
+  <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="CURRENT_ST_12" />
+  <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_15_C1" />
+  <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="CURRENT_ST_12" />
+  <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="IN_OCT_40_CAL" />
+  <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="IO_STD_SSTL_15" />
+  <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
+  <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="IO_STD_LVDS" />
+  <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
+  <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="IO_STD_CMOS_15" />
+  <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+  <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_DDR4_DEFAULT_IO" value="true" />
+  <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
+  <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1200.0" />
+  <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
+  <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+  <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
+  <parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
+  <parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
+  <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_LPDDR3_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_LPDDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_LPDDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+  <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
+  <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
+  <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
+  <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
+  <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+  <parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
+  <parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
+  <parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
+  <parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
+  <parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+  <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
+  <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
+  <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
+  <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
+  <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
+  <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
+  <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
+  <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+  <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
+  <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
+  <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
+  <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR3" />
+  <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="true" />
+  <parameter name="SYS_INFO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_sys_ddr3_cntrl</parameter>
+  <parameter name="TRAIT_SUPPORTS_VID" value="0" />
+ </module>
+ <module name="sys_ethernet" kind="altera_eth_tse" version="15.1" enabled="1">
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="core_variation" value="MAC_PCS" />
+  <parameter name="deviceFamilyName" value="Arria 10" />
+  <parameter name="eg_addr" value="12" />
+  <parameter name="ena_hash" value="false" />
+  <parameter name="enable_alt_reconfig" value="false" />
+  <parameter name="enable_ecc" value="false" />
+  <parameter name="enable_ena" value="32" />
+  <parameter name="enable_gmii_loopback" value="false" />
+  <parameter name="enable_hd_logic" value="false" />
+  <parameter name="enable_mac_flow_ctrl" value="false" />
+  <parameter name="enable_mac_vlan" value="false" />
+  <parameter name="enable_magic_detect" value="true" />
+  <parameter name="enable_ptp_1step" value="false" />
+  <parameter name="enable_sgmii" value="true" />
+  <parameter name="enable_shift16" value="true" />
+  <parameter name="enable_sup_addr" value="false" />
+  <parameter name="enable_timestamping" value="false" />
+  <parameter name="enable_use_internal_fifo" value="true" />
+  <parameter name="export_pwrdn" value="false" />
+  <parameter name="ext_stat_cnt_ena" value="false" />
+  <parameter name="ifGMII" value="MII_GMII" />
+  <parameter name="ing_addr" value="12" />
+  <parameter name="max_channels" value="1" />
+  <parameter name="mdio_clk_div" value="40" />
+  <parameter name="nf_phyip_rcfg_enable" value="false" />
+  <parameter name="phy_identifier" value="0" />
+  <parameter name="phyip_en_synce_support" value="false" />
+  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+  <parameter name="phyip_pll_type" value="CMU" />
+  <parameter name="phyip_pma_bonding_mode" value="x1" />
+  <parameter name="starting_channel_number" value="0" />
+  <parameter name="stat_cnt_ena" value="true" />
+  <parameter name="transceiver_type" value="LVDS_IO" />
+  <parameter name="tstamp_fp_width" value="4" />
+  <parameter name="useMDIO" value="true" />
+  <parameter name="use_mac_clken" value="false" />
+  <parameter name="use_misc_ports" value="true" />
+ </module>
+ <module
+   name="sys_ethernet_dma_rx"
+   kind="altera_msgdma"
+   version="15.1"
+   enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="BURST_ENABLE" value="1" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="256" />
+  <parameter name="DATA_WIDTH" value="64" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
+  <parameter name="ENHANCED_FEATURES" value="1" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="6" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="64" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="2" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="0" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="0" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module
+   name="sys_ethernet_dma_tx"
+   kind="altera_msgdma"
+   version="15.1"
+   enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="BURST_ENABLE" value="1" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="256" />
+  <parameter name="DATA_WIDTH" value="64" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="512" />
+  <parameter name="ENHANCED_FEATURES" value="1" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="64" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="1" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="0" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="2" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module
+   name="sys_ethernet_reset"
+   kind="altera_reset_bridge"
+   version="15.1"
+   enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module
+   name="sys_gpio_bd"
+   kind="altera_avalon_pio"
+   version="15.1"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="InOut" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_gpio_in"
+   kind="altera_avalon_pio"
+   version="15.1"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_gpio_out"
+   kind="altera_avalon_pio"
+   version="15.1"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module
+   name="sys_id"
+   kind="altera_avalon_sysid_qsys"
+   version="15.1"
+   enabled="1">
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="id" value="182193580" />
+ </module>
+ <module
+   name="sys_int_mem"
+   kind="altera_avalon_onchip_memory2"
+   version="15.1"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="deviceFamily" value="Arria 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="163840" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="sys_irq" kind="altera_irq_bridge" version="15.1" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_RECEIVER_IRQ_INTERRUPTS_USED" value="0" />
+  <parameter name="IRQ_N" value="0" />
+  <parameter name="IRQ_WIDTH" value="8" />
+ </module>
+ <module
+   name="sys_mem_interconnect"
+   kind="altera_avalon_mm_bridge"
+   version="15.1"
+   enabled="1">
+  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
+  <parameter name="ADDRESS_WIDTH" value="29" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="133333250" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="DATA_WIDTH" value="512" />
+  <parameter name="LINEWRAPBURSTS" value="0" />
+  <parameter name="MAX_BURST_SIZE" value="1" />
+  <parameter name="MAX_PENDING_RESPONSES" value="4" />
+  <parameter name="PIPELINE_COMMAND" value="1" />
+  <parameter name="PIPELINE_RESPONSE" value="1" />
+  <parameter name="SYMBOL_WIDTH" value="8" />
+  <parameter name="SYSINFO_ADDR_WIDTH" value="28" />
+  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
+  <parameter name="USE_RESPONSE" value="0" />
+ </module>
+ <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module name="sys_spi" kind="altera_avalon_spi" version="15.1" enabled="1">
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clockPhase" value="0" />
+  <parameter name="clockPolarity" value="0" />
+  <parameter name="dataWidth" value="8" />
+  <parameter name="disableAvalonFlowControl" value="false" />
+  <parameter name="inputClockRate" value="100000000" />
+  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
+  <parameter name="insertSync" value="false" />
+  <parameter name="lsbOrderedFirst" value="false" />
+  <parameter name="masterSPI" value="true" />
+  <parameter name="numberOfSlaves" value="8" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="targetClockRate" value="128000" />
+  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
+ </module>
+ <module
+   name="sys_timer"
+   kind="altera_avalon_timer"
+   version="15.1"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="100000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="sys_timer_2nd"
+   kind="altera_avalon_timer"
+   version="15.1"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="100000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="sys_tlb_mem"
+   kind="altera_avalon_onchip_memory2"
+   version="15.1"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_sys_tlb_mem</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="deviceFamily" value="Arria 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+  <parameter name="dualPort" value="true" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="163840" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module
+   name="sys_uart"
+   kind="altera_avalon_jtag_uart"
+   version="15.1"
+   enabled="1">
+  <parameter name="allowMultipleConnections" value="false" />
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clkFreq" value="100000000" />
+  <parameter name="hubInstanceID" value="0" />
+  <parameter name="readBufferDepth" value="64" />
+  <parameter name="readIRQThreshold" value="8" />
+  <parameter name="simInputCharacterStream" value="" />
+  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
+  <parameter name="useRegistersForReadBuffer" value="false" />
+  <parameter name="useRegistersForWriteBuffer" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="writeBufferDepth" value="64" />
+  <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_uart.avalon_jtag_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814f0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ethernet.control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_id.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814e8" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814a0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_tx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181480" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ddr3_cntrl.ctrl_amm_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10180800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_tx.descriptor_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181460" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.descriptor_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181440" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.response">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814e0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_cpu_interconnect.s0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10140000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_timer.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181420" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_gpio_bd.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814d0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_gpio_in.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x101814c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_gpio_out.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181500" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_timer_2nd.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181520" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.data_master"
+   end="sys_spi.spi_control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10181400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.instruction_master"
+   end="sys_ddr3_cntrl.ctrl_amm_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.instruction_master"
+   end="sys_cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10180800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.instruction_master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10140000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_mem_interconnect.m0"
+   end="sys_ddr3_cntrl.ctrl_amm_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_ethernet_dma_tx.mm_read"
+   end="sys_ddr3_cntrl.ctrl_amm_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_ethernet_dma_rx.mm_write"
+   end="sys_ddr3_cntrl.ctrl_amm_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.tightly_coupled_data_master_0"
+   end="sys_tlb_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
+   start="sys_cpu.tightly_coupled_instruction_master_0"
+   end="sys_tlb_mem.s2">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x10200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon_streaming"
+   version="15.1"
+   start="sys_ethernet.receive"
+   end="sys_ethernet_dma_rx.st_sink" />
+ <connection
+   kind="avalon_streaming"
+   version="15.1"
+   start="sys_ethernet_dma_tx.st_source"
+   end="sys_ethernet.transmit" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_ddr3_cntrl.emif_usr_clk"
+   end="sys_mem_interconnect.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_ddr3_cntrl.emif_usr_clk"
+   end="mem_rst.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_ddr3_cntrl.emif_usr_clk"
+   end="mem_clk.in_clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_cpu.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_uart.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_timer.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_id.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_gpio_bd.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_spi.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_cpu_interconnect.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_irq.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_ethernet_reset.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_gpio_in.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_gpio_out.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_timer_2nd.clk" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_int_mem.clk1" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_tlb_mem.clk1" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_tlb_mem.clk2" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_ethernet_dma_rx.clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_ethernet_dma_tx.clock" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_ethernet.control_port_clock_connection" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_ethernet.receive_clock_connection" />
+ <connection
+   kind="clock"
+   version="15.1"
+   start="sys_clk.out_clk"
+   end="sys_ethernet.transmit_clock_connection" />
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_ethernet_dma_rx.csr_irq">
+  <parameter name="irqNumber" value="3" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_ethernet_dma_tx.csr_irq">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_uart.irq">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_timer.irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection kind="interrupt" version="15.1" start="sys_cpu.irq" end="sys_spi.irq">
+  <parameter name="irqNumber" value="4" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_gpio_bd.irq">
+  <parameter name="irqNumber" value="5" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_gpio_in.irq">
+  <parameter name="irqNumber" value="8" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_timer_2nd.irq">
+  <parameter name="irqNumber" value="15" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender0_irq">
+  <parameter name="irqNumber" value="6" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender1_irq">
+  <parameter name="irqNumber" value="7" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender2_irq">
+  <parameter name="irqNumber" value="9" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender3_irq">
+  <parameter name="irqNumber" value="10" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender4_irq">
+  <parameter name="irqNumber" value="11" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender5_irq">
+  <parameter name="irqNumber" value="12" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender6_irq">
+  <parameter name="irqNumber" value="13" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.1"
+   start="sys_cpu.irq"
+   end="sys_irq.sender7_irq">
+  <parameter name="irqNumber" value="14" />
+ </connection>
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_cpu.debug_reset_request"
+   end="sys_cpu.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_ddr3_cntrl.emif_usr_reset_n"
+   end="mem_rst.in_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_ddr3_cntrl.emif_usr_reset_n"
+   end="sys_mem_interconnect.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_irq.clk_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_ddr3_cntrl.global_reset_n" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_ethernet_reset.in_reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_cpu.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_uart.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_timer.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_id.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_gpio_bd.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_spi.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_cpu_interconnect.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_gpio_in.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_gpio_out.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_timer_2nd.reset" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_int_mem.reset1" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_tlb_mem.reset1" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_tlb_mem.reset2" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_ethernet.reset_connection" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_ethernet_dma_rx.reset_n" />
+ <connection
+   kind="reset"
+   version="15.1"
+   start="sys_rst.out_reset"
+   end="sys_ethernet_dma_tx.reset_n" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+</system>