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daq2/kc705- adxcvr changes

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Rejeesh Kutty 2016-08-16 12:47:19 -04:00
parent 8464816c82
commit 8311098384
3 changed files with 22 additions and 10 deletions
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5
projects/daq2/kc705/system_bd.tcl
View File

@ -1,8 +1,9 @@
source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
source ../common/daq2_bd.tcl

5
projects/daq2/kc705/system_constr.xdc
View File

@ -56,5 +56,6 @@ set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_po
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]

22
projects/daq2/kc705/system_top.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -374,8 +372,14 @@ module system_top (
.mii_tx_clk (mii_tx_clk),
.mii_tx_en (mii_tx_en),
.mii_txd (mii_txd),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
@ -389,8 +393,14 @@ module system_top (
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.tx_data_n (tx_data_n),
.tx_data_p (tx_data_p),
.tx_data_0_n (tx_data_n[0]),
.tx_data_0_p (tx_data_p[0]),
.tx_data_1_n (tx_data_n[1]),
.tx_data_1_p (tx_data_p[1]),
.tx_data_2_n (tx_data_n[2]),
.tx_data_2_p (tx_data_p[2]),
.tx_data_3_n (tx_data_n[3]),
.tx_data_3_p (tx_data_p[3]),
.tx_ref_clk (tx_ref_clk),
.tx_sync (tx_sync),
.tx_sysref (tx_sysref),