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axi_dmac: dest_axi_mm: Use fixed wstrb signal 

The DMAC currently doesn't support transfers where the length is not a
multiple of the bus width. When generating the wstrb signal we do pretend
though that we do and dynamically generate it based on the LSBs of the
transfer length.

Given that the other parts of the DMA don't support such transfers this is
unnecessary though. So remove it for now and replace it with a constant
expression where wstrb is always fully asserted.

The generated logic for the wstrb signal was quite terrible, so this
improves the timing of the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-07-28 19:10:18 +02:00
parent aeabe91144
commit 834eb6aaa5
2 changed files with 4 additions and 20 deletions
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14
library/axi_dmac/dest_axi_mm.v
View File

@ -49,7 +49,6 @@ module dmac_dest_mm_axi #(
output req_ready, output req_ready,
input [DMA_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH] req_address, input [DMA_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH] req_address,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes,
input enable, input enable,
output enabled, output enabled,
@ -98,8 +97,6 @@ module dmac_dest_mm_axi #(
output m_axi_bready output m_axi_bready
); );
reg [(DMA_DATA_WIDTH/8)-1:0] wstrb;
wire address_req_valid; wire address_req_valid;
wire address_req_ready; wire address_req_ready;
wire data_req_valid; wire data_req_valid;
@ -196,16 +193,7 @@ dmac_data_mover # (
.m_axi_last(m_axi_wlast) .m_axi_last(m_axi_wlast)
); );
always @(*) assign m_axi_wstrb = {(DMA_DATA_WIDTH/8){1'b1}};
begin
if (data_eot & m_axi_wlast) begin
wstrb <= (1 << (req_last_beat_bytes + 1)) - 1;
end else begin
wstrb <= {(DMA_DATA_WIDTH/8){1'b1}};
end
end
assign m_axi_wstrb = wstrb;
dmac_response_handler #( dmac_response_handler #(
.ID_WIDTH(ID_WIDTH) .ID_WIDTH(ID_WIDTH)

10
library/axi_dmac/request_arb.v
View File

@ -215,7 +215,6 @@ wire dest_req_valid;
wire dest_req_ready; wire dest_req_ready;
wire [DMA_ADDRESS_WIDTH_DEST-1:0] dest_req_address; wire [DMA_ADDRESS_WIDTH_DEST-1:0] dest_req_address;
wire [BEATS_PER_BURST_WIDTH_DEST-1:0] dest_req_last_burst_length; wire [BEATS_PER_BURST_WIDTH_DEST-1:0] dest_req_last_burst_length;
wire [BYTES_PER_BEAT_WIDTH_DEST-1:0] dest_req_last_beat_bytes;
wire dest_req_xlast; wire dest_req_xlast;
wire dest_response_valid; wire dest_response_valid;
@ -416,7 +415,6 @@ dmac_dest_mm_axi #(
.req_ready(dest_req_ready), .req_ready(dest_req_ready),
.req_address(dest_req_address), .req_address(dest_req_address),
.req_last_burst_length(dest_req_last_burst_length), .req_last_burst_length(dest_req_last_burst_length),
.req_last_beat_bytes(dest_req_last_beat_bytes),
.response_valid(dest_response_valid), .response_valid(dest_response_valid),
.response_ready(dest_response_ready), .response_ready(dest_response_ready),
@ -957,7 +955,7 @@ splitter #(
); );
util_axis_fifo #( util_axis_fifo #(
.DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + BYTES_PER_BEAT_WIDTH_DEST + 1), .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + 1),
.ADDRESS_WIDTH(0), .ADDRESS_WIDTH(0),
.ASYNC_CLK(ASYNC_CLK_DEST_REQ) .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
) i_dest_req_fifo ( ) i_dest_req_fifo (
@ -969,8 +967,7 @@ util_axis_fifo #(
.s_axis_data({ .s_axis_data({
req_dest_address, req_dest_address,
req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST], req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST],
req_length[BYTES_PER_BEAT_WIDTH_DEST-1:0], req_xlast
req_xlast
}), }),
.s_axis_room(), .s_axis_room(),
@ -981,8 +978,7 @@ util_axis_fifo #(
.m_axis_data({ .m_axis_data({
dest_req_address, dest_req_address,
dest_req_last_burst_length, dest_req_last_burst_length,
dest_req_last_beat_bytes, dest_req_xlast
dest_req_xlast
}), }),
.m_axis_level() .m_axis_level()
); );