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axi_dac_interpolate: Reduce filter_mask signal width 

Only the lower 3 bits of the filter_mask signal are used, no need to keep
the other bits around.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-04-10 10:50:02 +02:00
parent 9c2c50728c
commit 834fcb7e27
3 changed files with 25 additions and 25 deletions
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4
library/axi_dac_interpolate/axi_dac_interpolate.v
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@ -91,8 +91,8 @@ module axi_dac_interpolate(
wire [31:0] interpolation_ratio_a; wire [31:0] interpolation_ratio_a;
wire [31:0] interpolation_ratio_b; wire [31:0] interpolation_ratio_b;
wire [31:0] filter_mask_a; wire [ 2:0] filter_mask_a;
wire [31:0] filter_mask_b; wire [ 2:0] filter_mask_b;
wire dma_transfer_suspend; wire dma_transfer_suspend;

24
library/axi_dac_interpolate/axi_dac_interpolate_filter.v
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@ -48,7 +48,7 @@ module axi_dac_interpolate_filter (
output reg [15:0] dac_int_data, output reg [15:0] dac_int_data,
output reg dac_int_valid, output reg dac_int_valid,
input [31:0] filter_mask, input [ 2:0] filter_mask,
input [31:0] interpolation_ratio, input [31:0] interpolation_ratio,
input dma_transfer_suspend input dma_transfer_suspend
); );
@ -57,7 +57,7 @@ module axi_dac_interpolate_filter (
reg dac_filt_int_valid; reg dac_filt_int_valid;
reg [15:0] interp_rate_cic; reg [15:0] interp_rate_cic;
reg [31:0] filter_mask_d1; reg [ 2:0] filter_mask_d1;
reg cic_change_rate; reg cic_change_rate;
reg [31:0] interpolation_counter; reg [31:0] interpolation_counter;
@ -114,20 +114,20 @@ module axi_dac_interpolate_filter (
always @(*) begin always @(*) begin
case (filter_mask) case (filter_mask)
16'h1: dac_int_data = dac_cic_data[31:16]; 3'h1: dac_int_data = dac_cic_data[31:16];
16'h2: dac_int_data = dac_cic_data[31:16]; 3'h2: dac_int_data = dac_cic_data[31:16];
16'h3: dac_int_data = dac_cic_data[31:16]; 3'h3: dac_int_data = dac_cic_data[31:16];
16'h6: dac_int_data = dac_cic_data[31:16]; 3'h6: dac_int_data = dac_cic_data[31:16];
16'h7: dac_int_data = dac_cic_data[31:16]; 3'h7: dac_int_data = dac_cic_data[31:16];
default: dac_int_data = dac_data; default: dac_int_data = dac_data;
endcase endcase
case (filter_mask) case (filter_mask)
16'h1: dac_filt_int_valid = dac_fir_valid; 3'h1: dac_filt_int_valid = dac_fir_valid;
16'h2: dac_filt_int_valid = dac_fir_valid; 3'h2: dac_filt_int_valid = dac_fir_valid;
16'h3: dac_filt_int_valid = dac_fir_valid; 3'h3: dac_filt_int_valid = dac_fir_valid;
16'h6: dac_filt_int_valid = dac_fir_valid; 3'h6: dac_filt_int_valid = dac_fir_valid;
16'h7: dac_filt_int_valid = dac_fir_valid; 3'h7: dac_filt_int_valid = dac_fir_valid;
default: dac_filt_int_valid = dac_valid & !dma_transfer_suspend; default: dac_filt_int_valid = dac_valid & !dma_transfer_suspend;
endcase endcase

22
library/axi_dac_interpolate/axi_dac_interpolate_reg.v
View File

@ -42,9 +42,9 @@ module axi_dac_interpolate_reg(
input clk, input clk,
output [31:0] dac_interpolation_ratio_a, output [31:0] dac_interpolation_ratio_a,
output [31:0] dac_filter_mask_a, output [ 2:0] dac_filter_mask_a,
output [31:0] dac_interpolation_ratio_b, output [31:0] dac_interpolation_ratio_b,
output [31:0] dac_filter_mask_b, output [ 2:0] dac_filter_mask_b,
output dma_transfer_suspend, output dma_transfer_suspend,
// bus interface // bus interface
@ -71,9 +71,9 @@ module axi_dac_interpolate_reg(
reg [31:0] up_scratch = 32'h0; reg [31:0] up_scratch = 32'h0;
reg [31:0] up_interpolation_ratio_a = 32'h0; reg [31:0] up_interpolation_ratio_a = 32'h0;
reg [31:0] up_filter_mask_a = 32'h0; reg [ 2:0] up_filter_mask_a = 3'h0;
reg [31:0] up_interpolation_ratio_b = 32'h0; reg [31:0] up_interpolation_ratio_b = 32'h0;
reg [31:0] up_filter_mask_b = 32'h0; reg [ 2:0] up_filter_mask_b = 3'h0;
reg [31:0] up_flags = 32'h0; reg [31:0] up_flags = 32'h0;
assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0; assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0;
@ -97,13 +97,13 @@ module axi_dac_interpolate_reg(
up_interpolation_ratio_a <= up_wdata; up_interpolation_ratio_a <= up_wdata;
end end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h11)) begin if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
up_filter_mask_a <= up_wdata; up_filter_mask_a <= up_wdata[2:0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h12)) begin if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
up_interpolation_ratio_b <= up_wdata; up_interpolation_ratio_b <= up_wdata;
end end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h13)) begin if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
up_filter_mask_b <= up_wdata; up_filter_mask_b <= up_wdata[2:0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h14)) begin if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
up_flags <= up_wdata; up_flags <= up_wdata;
@ -136,14 +136,14 @@ module axi_dac_interpolate_reg(
end end
end end
up_xfer_cntrl #(.DATA_WIDTH(129)) i_xfer_cntrl ( up_xfer_cntrl #(.DATA_WIDTH(71)) i_xfer_cntrl (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_cntrl ({ up_flags[0], // 1 .up_data_cntrl ({ up_flags[0], // 1
up_interpolation_ratio_b, // 32 up_interpolation_ratio_b, // 32
up_interpolation_ratio_a, // 32 up_interpolation_ratio_a, // 32
up_filter_mask_b, // 32 up_filter_mask_b, // 3
up_filter_mask_a}), // 32 up_filter_mask_a}), // 3
.up_xfer_done (), .up_xfer_done (),
.d_rst (1'b0), .d_rst (1'b0),
@ -151,8 +151,8 @@ module axi_dac_interpolate_reg(
.d_data_cntrl ({ dma_transfer_suspend, // 1 .d_data_cntrl ({ dma_transfer_suspend, // 1
dac_interpolation_ratio_b, // 32 dac_interpolation_ratio_b, // 32
dac_interpolation_ratio_a, // 32 dac_interpolation_ratio_a, // 32
dac_filter_mask_b, // 32 dac_filter_mask_b, // 3
dac_filter_mask_a})); // 32 dac_filter_mask_a})); // 3
endmodule endmodule