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ad_serdes_in: Add CMOS support

main
Laszlo Nagy 2020-04-28 13:41:47 +01:00 committed by Laszlo Nagy
parent e6b9e21ad1
commit 837475db0d
1 changed files with 16 additions and 10 deletions
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22
library/xilinx/common/ad_serdes_in.v
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@ -38,6 +38,7 @@
module ad_serdes_in #( module ad_serdes_in #(
parameter FPGA_TECHNOLOGY = 0, parameter FPGA_TECHNOLOGY = 0,
parameter CMOS_LVDS_N = 0,
parameter DDR_OR_SDR_N = 0, parameter DDR_OR_SDR_N = 0,
parameter SERDES_FACTOR = 8, parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16, parameter DATA_WIDTH = 16,
@ -120,15 +121,24 @@ module ad_serdes_in #(
endgenerate endgenerate
// received data interface: ibuf -> idelay -> iserdes // received data interface: ibuf -> idelay -> iserdes
genvar l_inst; genvar l_inst;
generate if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin generate
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_io
if (CMOS_LVDS_N == 0) begin
IBUFDS i_ibuf ( IBUFDS i_ibuf (
.I (data_in_p[l_inst]), .I (data_in_p[l_inst]),
.IB (data_in_n[l_inst]), .IB (data_in_n[l_inst]),
.O (data_in_ibuf_s[l_inst])); .O (data_in_ibuf_s[l_inst]));
end else begin
IBUF i_ibuf (
.I (data_in_p[l_inst]),
.O (data_in_ibuf_s[l_inst]));
end
end
endgenerate
generate if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
(* IODELAY_GROUP = IODELAY_GROUP *) (* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE2 #( IDELAYE2 #(
@ -210,10 +220,6 @@ module ad_serdes_in #(
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
IBUFDS i_ibuf (
.I (data_in_p[l_inst]),
.IB (data_in_n[l_inst]),
.O (data_in_ibuf_s[l_inst]));
wire div_dld; wire div_dld;
reg [4:0] vtc_cnt = {5{1'b1}}; reg [4:0] vtc_cnt = {5{1'b1}};