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axi_adc_decimate: Reduce AXI address width 

The axi_adc_decimate does not use the full width of the AXI interface
address. It only responds to register access in the first 32 registers.

Reduce the size of the AXI address to 7 bit accordingly. This allows the
scripts to correctly infer the internal register map size which will cause
the interconnect to filter out access to these unused register.

This slightly reduces utilization by getting rid of some pipeline
registers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-04-10 19:30:38 +02:00
parent 53c8ece8f8
commit 837b2c02e2
2 changed files with 16 additions and 21 deletions
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13
library/axi_adc_decimate/axi_adc_decimate.v
View File

@ -57,7 +57,7 @@ module axi_adc_decimate(
input s_axi_aclk, input s_axi_aclk,
input s_axi_aresetn, input s_axi_aresetn,
input s_axi_awvalid, input s_axi_awvalid,
input [31:0] s_axi_awaddr, input [ 6:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot, input [ 2:0] s_axi_awprot,
output s_axi_awready, output s_axi_awready,
input s_axi_wvalid, input s_axi_wvalid,
@ -68,7 +68,7 @@ module axi_adc_decimate(
output [ 1:0] s_axi_bresp, output [ 1:0] s_axi_bresp,
input s_axi_bready, input s_axi_bready,
input s_axi_arvalid, input s_axi_arvalid,
input [31:0] s_axi_araddr, input [ 6:0] s_axi_araddr,
input [ 2:0] s_axi_arprot, input [ 2:0] s_axi_arprot,
output s_axi_arready, output s_axi_arready,
output s_axi_rvalid, output s_axi_rvalid,
@ -80,14 +80,14 @@ module axi_adc_decimate(
wire up_clk; wire up_clk;
wire up_rstn; wire up_rstn;
wire [13:0] up_waddr; wire [ 4:0] up_waddr;
wire [31:0] up_wdata; wire [31:0] up_wdata;
wire up_wack; wire up_wack;
wire up_wreq; wire up_wreq;
wire up_rack; wire up_rack;
wire [31:0] up_rdata; wire [31:0] up_rdata;
wire up_rreq; wire up_rreq;
wire [13:0] up_raddr; wire [ 4:0] up_raddr;
wire [31:0] decimation_ratio; wire [31:0] decimation_ratio;
wire [ 2:0] filter_mask; wire [ 2:0] filter_mask;
@ -132,7 +132,10 @@ module axi_adc_decimate(
.up_rdata (up_rdata), .up_rdata (up_rdata),
.up_rack (up_rack)); .up_rack (up_rack));
up_axi i_up_axi ( up_axi #(
.AXI_ADDRESS_WIDTH(7),
.ADDRESS_WIDTH(5)
) i_up_axi (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid), .up_axi_awvalid (s_axi_awvalid),

24
library/axi_adc_decimate/axi_adc_decimate_reg.v
View File

@ -49,19 +49,14 @@ module axi_adc_decimate_reg(
input up_rstn, input up_rstn,
input up_clk, input up_clk,
input up_wreq, input up_wreq,
input [13:0] up_waddr, input [ 4:0] up_waddr,
input [31:0] up_wdata, input [31:0] up_wdata,
output reg up_wack, output reg up_wack,
input up_rreq, input up_rreq,
input [13:0] up_raddr, input [ 4:0] up_raddr,
output reg [31:0] up_rdata, output reg [31:0] up_rdata,
output reg up_rack); output reg up_rack);
// internal signals
wire up_wreq_s;
wire up_rreq_s;
// internal registers // internal registers
reg [31:0] up_version = 32'h00010000; reg [31:0] up_version = 32'h00010000;
@ -70,9 +65,6 @@ module axi_adc_decimate_reg(
reg [31:0] up_decimation_ratio = 32'h0; reg [31:0] up_decimation_ratio = 32'h0;
reg [ 2:0] up_filter_mask = 32'h0; reg [ 2:0] up_filter_mask = 32'h0;
assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0;
assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_wack <= 'd0; up_wack <= 'd0;
@ -80,14 +72,14 @@ module axi_adc_decimate_reg(
up_decimation_ratio <= 'd0; up_decimation_ratio <= 'd0;
up_filter_mask <= 'd0; up_filter_mask <= 'd0;
end else begin end else begin
up_wack <= up_wreq_s; up_wack <= up_wreq;
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
up_scratch <= up_wdata; up_scratch <= up_wdata;
end end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h10)) begin if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
up_decimation_ratio <= up_wdata; up_decimation_ratio <= up_wdata;
end end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h11)) begin if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
up_filter_mask <= up_wdata[2:0]; up_filter_mask <= up_wdata[2:0];
end end
end end
@ -100,8 +92,8 @@ module axi_adc_decimate_reg(
up_rack <= 'd0; up_rack <= 'd0;
up_rdata <= 'd0; up_rdata <= 'd0;
end else begin end else begin
up_rack <= up_rreq_s; up_rack <= up_rreq;
if (up_rreq_s == 1'b1) begin if (up_rreq == 1'b1) begin
case (up_raddr[4:0]) case (up_raddr[4:0])
5'h0: up_rdata <= up_version; 5'h0: up_rdata <= up_version;
5'h1: up_rdata <= up_scratch; 5'h1: up_rdata <= up_scratch;