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daq3: Update projects to the new TPL 

Also modified the FIFO ports to have the same widths so that in a
future commit the bypass would be available for cases when the
sampling rate won't be the maximum rate or the number of channels
active will be less than maximum number of channels
main
Adrian Costina 2020-10-17 15:15:02 +01:00
parent 9f58b465ea
commit 83cebe899f
2 changed files with 141 additions and 89 deletions
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137
projects/daq3/common/daq3_bd.tcl
View File

@ -1,61 +1,83 @@
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
set adc_fifo_name axi_ad9680_fifo
set adc_data_width 128
set adc_dma_data_width 64
# TX parameters
set TX_NUM_OF_LANES 4 ; # L
set TX_NUM_OF_CONVERTERS 2 ; # M
set TX_SAMPLES_PER_FRAME 1 ; # S
set TX_SAMPLE_WIDTH 16 ; # N/NP
set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / \
($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
set dac_fifo_name axi_ad9152_fifo
set dac_data_width 128
set dac_dma_data_width 128
set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
# RX parameters
set RX_NUM_OF_LANES 4 ; # L
set RX_NUM_OF_CONVERTERS 2 ; # M
set RX_SAMPLES_PER_FRAME 1 ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP
set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / \
($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
set adc_fifo_name axi_ad9680_fifo
set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
# dac peripherals
ad_ip_instance axi_adxcvr axi_ad9152_xcvr
ad_ip_parameter axi_ad9152_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9152_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter axi_ad9152_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9152_xcvr CONFIG.TX_OR_RX_N 1
adi_axi_jesd204_tx_create axi_ad9152_jesd 4
adi_axi_jesd204_tx_create axi_ad9152_jesd $TX_NUM_OF_LANES
ad_ip_instance axi_ad9152 axi_ad9152_core
adi_tpl_jesd204_tx_create axi_ad9152_tpl_core $TX_NUM_OF_LANES \
$TX_NUM_OF_CONVERTERS \
$TX_SAMPLES_PER_FRAME \
$TX_SAMPLE_WIDTH
ad_ip_instance util_upack2 axi_ad9152_upack { \
NUM_OF_CHANNELS 2 \
SAMPLES_PER_CHANNEL 4 \
SAMPLE_DATA_WIDTH 16 \
}
ad_ip_instance util_upack2 axi_ad9152_upack [list \
NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
]
ad_ip_instance axi_dmac axi_ad9152_dma
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_ad9152_dma CONFIG.ID 1
ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_SRC 1
ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9152_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width
# adc peripherals
ad_ip_instance axi_adxcvr axi_ad9680_xcvr
ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0
adi_axi_jesd204_rx_create axi_ad9680_jesd 4
adi_axi_jesd204_rx_create axi_ad9680_jesd $RX_NUM_OF_LANES
ad_ip_instance axi_ad9680 axi_ad9680_core
adi_tpl_jesd204_rx_create axi_ad9680_tpl_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH
ad_ip_instance util_cpack2 axi_ad9680_cpack { \
NUM_OF_CHANNELS 2 \
SAMPLE_DATA_WIDTH 16 \
SAMPLES_PER_CHANNEL 4 \
}
ad_ip_instance util_cpack2 axi_ad9680_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
]
ad_ip_instance axi_dmac axi_ad9680_dma
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
@ -67,18 +89,18 @@ ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_data_width
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_data_width $adc_fifo_address_width
}
# shared transceiver core
ad_ip_instance util_adxcvr util_daq3_xcvr
ad_ip_parameter util_daq3_xcvr CONFIG.RX_NUM_OF_LANES 4
ad_ip_parameter util_daq3_xcvr CONFIG.TX_NUM_OF_LANES 4
ad_ip_parameter util_daq3_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter util_daq3_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV_RATIO 1
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 0x30; # 20
@ -103,22 +125,22 @@ ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq3_xcvr/up_cpll_rst_*
# connections (dac)
ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd {0 2 3 1}
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_core/tx_clk
ad_connect axi_ad9152_jesd/tx_data_tdata axi_ad9152_core/tx_data
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_tpl_core/link_clk
ad_connect axi_ad9152_jesd/tx_data axi_ad9152_tpl_core/link
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/clk
ad_connect axi_ad9152_jesd_rstgen/peripheral_reset axi_ad9152_upack/reset
ad_connect axi_ad9152_core/dac_valid_0 axi_ad9152_upack/fifo_rd_en
for {set i 0} {$i < 2} {incr i} {
ad_connect axi_ad9152_core/dac_enable_$i axi_ad9152_upack/enable_$i
ad_connect axi_ad9152_core/dac_ddata_$i axi_ad9152_upack/fifo_rd_data_$i
ad_connect axi_ad9152_tpl_core/dac_valid_0 axi_ad9152_upack/fifo_rd_en
for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
ad_connect axi_ad9152_tpl_core/dac_enable_$i axi_ad9152_upack/enable_$i
ad_connect axi_ad9152_tpl_core/dac_data_$i axi_ad9152_upack/fifo_rd_data_$i
}
if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_connect $sys_cpu_clk axi_ad9152_fifo/dma_clk
ad_connect $sys_cpu_reset axi_ad9152_fifo/dma_rst
ad_connect $sys_cpu_clk axi_ad9152_dma/m_axis_aclk
ad_connect $sys_cpu_resetn axi_ad9152_dma/m_src_axi_aresetn
ad_connect $sys_dma_clk axi_ad9152_fifo/dma_clk
ad_connect $sys_dma_reset axi_ad9152_fifo/dma_rst
ad_connect $sys_dma_clk axi_ad9152_dma/m_axis_aclk
ad_connect $sys_dma_resetn axi_ad9152_dma/m_src_axi_aresetn
ad_connect axi_ad9152_fifo/bypass GND
}
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk
@ -129,7 +151,7 @@ ad_connect axi_ad9152_upack/s_axis_valid VCC
ad_connect axi_ad9152_upack/s_axis_ready axi_ad9152_fifo/dac_valid
ad_connect axi_ad9152_upack/s_axis_data axi_ad9152_fifo/dac_data
ad_connect axi_ad9152_core/dac_dunf axi_ad9152_fifo/dac_dunf
ad_connect axi_ad9152_tpl_core/dac_dunf axi_ad9152_fifo/dac_dunf
ad_connect axi_ad9152_fifo/dma_xfer_req axi_ad9152_dma/m_axis_xfer_req
ad_connect axi_ad9152_fifo/dma_ready axi_ad9152_dma/m_axis_ready
ad_connect axi_ad9152_fifo/dma_data axi_ad9152_dma/m_axis_data
@ -139,51 +161,52 @@ ad_connect axi_ad9152_fifo/dma_xfer_last axi_ad9152_dma/m_axis_last
# connections (adc)
ad_xcvrcon util_daq3_xcvr axi_ad9680_xcvr axi_ad9680_jesd
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core/rx_sof
ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_core/rx_data
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_tpl_core/link_clk
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_tpl_core/link_sof
ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_tpl_core/link_data
ad_connect axi_ad9680_jesd/rx_data_tvalid axi_ad9680_tpl_core/link_valid
ad_connect axi_ad9680_tpl_core/adc_valid_0 axi_ad9680_cpack/fifo_wr_en
if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_fifo/adc_wdata
ad_connect $sys_cpu_clk axi_ad9680_fifo/dma_clk
ad_connect $sys_cpu_clk axi_ad9680_dma/s_axis_aclk
ad_connect $sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
ad_connect $sys_dma_clk axi_ad9680_fifo/dma_clk
ad_connect $sys_dma_clk axi_ad9680_dma/s_axis_aclk
ad_connect $sys_dma_resetn axi_ad9680_dma/m_dest_axi_aresetn
ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
ad_connect axi_ad9680_tpl_core/adc_dovf axi_ad9680_fifo/adc_wovf
}
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/reset
ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/fifo_wr_en
for {set i 0} {$i < 2} {incr i} {
ad_connect axi_ad9680_core/adc_enable_$i axi_ad9680_cpack/enable_$i
ad_connect axi_ad9680_core/adc_data_$i axi_ad9680_cpack/fifo_wr_data_$i
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect axi_ad9680_tpl_core/adc_enable_$i axi_ad9680_cpack/enable_$i
ad_connect axi_ad9680_tpl_core/adc_data_$i axi_ad9680_cpack/fifo_wr_data_$i
}
# interconnect (cpu)
ad_cpu_interconnect 0x44A60000 axi_ad9152_xcvr
ad_cpu_interconnect 0x44A04000 axi_ad9152_core
ad_cpu_interconnect 0x44A04000 axi_ad9152_tpl_core
ad_cpu_interconnect 0x44A90000 axi_ad9152_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9152_dma
ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
ad_cpu_interconnect 0x44A10000 axi_ad9680_core
ad_cpu_interconnect 0x44A10000 axi_ad9680_tpl_core
ad_cpu_interconnect 0x44AA0000 axi_ad9680_jesd
ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9152_dma/m_src_axi
ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9680_dma/m_dest_axi
ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_dma_clk axi_ad9152_dma/m_src_axi
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9680_dma/m_dest_axi
ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9680_xcvr/m_axi
}

93
projects/daq3/common/daq3_qsys.tcl
View File

@ -1,6 +1,23 @@
# JESD204B attributes
set RX_NUM_OF_LANES 4 ; # L
set RX_NUM_OF_CONVERTERS 2 ; # M
set RX_SAMPLES_PER_FRAME 1 ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP
set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]
set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
set TX_NUM_OF_LANES 4 ; # L
set TX_NUM_OF_CONVERTERS 2 ; # M
set TX_SAMPLES_PER_FRAME 1 ; # S
set TX_SAMPLE_WIDTH 16 ; # N/NP
set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)]
set dac_fifo_name avl_ad9152_fifo
set dac_data_width 128
set dac_dma_data_width 128
# ad9152-xcvr
@ -9,7 +26,7 @@ set_instance_parameter_value ad9152_jesd204 {ID} {0}
set_instance_parameter_value ad9152_jesd204 {TX_OR_RX_N} {1}
set_instance_parameter_value ad9152_jesd204 {LANE_RATE} {12333.3}
set_instance_parameter_value ad9152_jesd204 {REFCLK_FREQUENCY} {616.665}
set_instance_parameter_value ad9152_jesd204 {NUM_OF_LANES} {4}
set_instance_parameter_value ad9152_jesd204 {NUM_OF_LANES} $TX_NUM_OF_LANES
set_instance_parameter_value ad9152_jesd204 {LANE_MAP} {0 3 1 2}
add_connection sys_clk.clk ad9152_jesd204.sys_clk
@ -25,29 +42,34 @@ set_interface_property tx_sync EXPORT_OF ad9152_jesd204.sync
# ad9152-core
add_instance axi_ad9152_core axi_ad9152
add_instance axi_ad9152_tpl ad_ip_jesd204_tpl_dac
set_instance_parameter_value axi_ad9152_tpl {ID} {0}
set_instance_parameter_value axi_ad9152_tpl {NUM_CHANNELS} $TX_NUM_OF_CONVERTERS
set_instance_parameter_value axi_ad9152_tpl {NUM_LANES} $TX_NUM_OF_LANES
set_instance_parameter_value axi_ad9152_tpl {BITS_PER_SAMPLE} $TX_SAMPLE_WIDTH
set_instance_parameter_value axi_ad9152_tpl {CONVERTER_RESOLUTION} $TX_SAMPLE_WIDTH
add_connection ad9152_jesd204.link_clk axi_ad9152_core.if_tx_clk
add_connection axi_ad9152_core.if_tx_data ad9152_jesd204.link_data
add_connection sys_clk.clk_reset axi_ad9152_core.s_axi_reset
add_connection sys_clk.clk axi_ad9152_core.s_axi_clock
add_connection ad9152_jesd204.link_clk axi_ad9152_tpl.link_clk
add_connection axi_ad9152_tpl.link_data ad9152_jesd204.link_data
add_connection sys_clk.clk_reset axi_ad9152_tpl.s_axi_reset
add_connection sys_clk.clk axi_ad9152_tpl.s_axi_clock
# ad9152-unpack
add_instance util_ad9152_upack util_upack2
set_instance_parameter_value util_ad9152_upack {NUM_OF_CHANNELS} {2}
set_instance_parameter_value util_ad9152_upack {SAMPLES_PER_CHANNEL} {4}
set_instance_parameter_value util_ad9152_upack {SAMPLE_DATA_WIDTH} {16}
set_instance_parameter_value util_ad9152_upack {NUM_OF_CHANNELS} $TX_NUM_OF_CONVERTERS
set_instance_parameter_value util_ad9152_upack {SAMPLES_PER_CHANNEL} $TX_SAMPLES_PER_CHANNEL
set_instance_parameter_value util_ad9152_upack {SAMPLE_DATA_WIDTH} $TX_SAMPLE_WIDTH
set_instance_parameter_value util_ad9152_upack {INTERFACE_TYPE} {1}
add_connection ad9152_jesd204.link_clk util_ad9152_upack.clk
add_connection ad9152_jesd204.link_reset util_ad9152_upack.reset
add_connection axi_ad9152_core.dac_ch_0 util_ad9152_upack.dac_ch_0
add_connection axi_ad9152_core.dac_ch_1 util_ad9152_upack.dac_ch_1
add_connection axi_ad9152_tpl.dac_ch_0 util_ad9152_upack.dac_ch_0
add_connection axi_ad9152_tpl.dac_ch_1 util_ad9152_upack.dac_ch_1
# dac fifo
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width
add_interface tx_fifo_bypass conduit end
set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9152_fifo.if_bypass
@ -56,15 +78,16 @@ add_connection ad9152_jesd204.link_clk avl_ad9152_fifo.if_dac_clk
add_connection ad9152_jesd204.link_reset avl_ad9152_fifo.if_dac_rst
add_connection util_ad9152_upack.if_packed_fifo_rd_en avl_ad9152_fifo.if_dac_valid
add_connection avl_ad9152_fifo.if_dac_data util_ad9152_upack.if_packed_fifo_rd_data
add_connection avl_ad9152_fifo.if_dac_dunf axi_ad9152_core.if_dac_dunf
add_connection avl_ad9152_fifo.if_dac_dunf axi_ad9152_tpl.if_dac_dunf
# ad9152-dma
add_instance axi_ad9152_dma axi_dmac
set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_SRC} {128}
set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_DEST} {128}
set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_DEST} $dac_data_width
set_instance_parameter_value axi_ad9152_dma {DMA_2D_TRANSFER} {0}
set_instance_parameter_value axi_ad9152_dma {SYNC_TRANSFER_START} {0}
set_instance_parameter_value axi_ad9152_dma {CYCLIC} {1}
set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_DEST} {1}
set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_SRC} {0}
set_instance_parameter_value axi_ad9152_dma {FIFO_SIZE} {16}
@ -103,31 +126,37 @@ set_interface_property rx_sync EXPORT_OF ad9680_jesd204.sync
# ad9680
add_instance axi_ad9680_core axi_ad9680
add_instance axi_ad9680_tpl ad_ip_jesd204_tpl_adc
set_instance_parameter_value axi_ad9680_tpl {ID} {0}
set_instance_parameter_value axi_ad9680_tpl {NUM_CHANNELS} $RX_NUM_OF_CONVERTERS
set_instance_parameter_value axi_ad9680_tpl {NUM_LANES} $RX_NUM_OF_LANES
set_instance_parameter_value axi_ad9680_tpl {BITS_PER_SAMPLE} $RX_SAMPLE_WIDTH
set_instance_parameter_value axi_ad9680_tpl {CONVERTER_RESOLUTION} $RX_SAMPLE_WIDTH
set_instance_parameter_value axi_ad9680_tpl {TWOS_COMPLEMENT} {1}
add_connection ad9680_jesd204.link_clk axi_ad9680_core.if_rx_clk
add_connection ad9680_jesd204.link_sof axi_ad9680_core.if_rx_sof
add_connection ad9680_jesd204.link_data axi_ad9680_core.if_rx_data
add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
add_connection ad9680_jesd204.link_clk axi_ad9680_tpl.link_clk
add_connection ad9680_jesd204.link_sof axi_ad9680_tpl.if_link_sof
add_connection ad9680_jesd204.link_data axi_ad9680_tpl.link_data
add_connection sys_clk.clk_reset axi_ad9680_tpl.s_axi_reset
add_connection sys_clk.clk axi_ad9680_tpl.s_axi_clock
# ad9680-pack
add_instance util_ad9680_cpack util_cpack2
set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2}
set_instance_parameter_value util_ad9680_cpack {SAMPLES_PER_CHANNEL} {4}
set_instance_parameter_value util_ad9680_cpack {SAMPLE_DATA_WIDTH} {16}
set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} $RX_NUM_OF_CONVERTERS
set_instance_parameter_value util_ad9680_cpack {SAMPLES_PER_CHANNEL} $RX_NUM_OF_LANES
set_instance_parameter_value util_ad9680_cpack {SAMPLE_DATA_WIDTH} $RX_SAMPLE_WIDTH
add_connection ad9680_jesd204.link_clk util_ad9680_cpack.clk
add_connection ad9680_jesd204.link_reset util_ad9680_cpack.reset
add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0
add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1
add_connection axi_ad9680_tpl.adc_ch_0 util_ad9680_cpack.adc_ch_0
add_connection axi_ad9680_tpl.adc_ch_1 util_ad9680_cpack.adc_ch_1
# ad9680-fifo
add_instance ad9680_adcfifo util_adcfifo
set_instance_parameter_value ad9680_adcfifo {ADC_DATA_WIDTH} {128}
set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} {128}
set_instance_parameter_value ad9680_adcfifo {ADC_DATA_WIDTH} $adc_data_width
set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} $adc_data_width
set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
@ -139,7 +168,7 @@ add_connection sys_clk.clk ad9680_adcfifo.if_dma_clk
# ad9680-dma
add_instance axi_ad9680_dma axi_dmac
set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_SRC} {128}
set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_SRC} $adc_data_width
set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_DEST} {128}
set_instance_parameter_value axi_ad9680_dma {DMA_LENGTH_WIDTH} {24}
set_instance_parameter_value axi_ad9680_dma {DMA_2D_TRANSFER} {0}
@ -151,7 +180,7 @@ set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1}
add_connection sys_clk.clk axi_ad9680_dma.if_s_axis_aclk
add_connection ad9680_adcfifo.m_axis axi_ad9680_dma.s_axis
add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req
add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf
add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_tpl.if_adc_dovf
add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset
add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock
add_connection sys_clk.clk_reset axi_ad9680_dma.m_dest_axi_reset
@ -178,7 +207,7 @@ ad_cpu_interconnect 0x00429000 avl_adxcfg_1.rcfg_s0
ad_cpu_interconnect 0x0042a000 avl_adxcfg_2.rcfg_s0
ad_cpu_interconnect 0x0042b000 avl_adxcfg_3.rcfg_s0
ad_cpu_interconnect 0x0042c000 axi_ad9152_dma.s_axi
ad_cpu_interconnect 0x00434000 axi_ad9152_core.s_axi
ad_cpu_interconnect 0x00434000 axi_ad9152_tpl.s_axi
ad_cpu_interconnect 0x00440000 ad9680_jesd204.link_reconfig
ad_cpu_interconnect 0x00444000 ad9680_jesd204.link_management
@ -188,7 +217,7 @@ ad_cpu_interconnect 0x00449000 avl_adxcfg_1.rcfg_s1
ad_cpu_interconnect 0x0044a000 avl_adxcfg_2.rcfg_s1
ad_cpu_interconnect 0x0044b000 avl_adxcfg_3.rcfg_s1
ad_cpu_interconnect 0x0044c000 axi_ad9680_dma.s_axi
ad_cpu_interconnect 0x00450000 axi_ad9680_core.s_axi
ad_cpu_interconnect 0x00450000 axi_ad9680_tpl.s_axi
# dma interconnects