ad9434_fmc: Update project to the new framework
Istvan Csomortani
parent
43673f6b9d
commit
8443e94442
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@ -1,25 +1,11 @@
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# ad9434 interface
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set adc_clk_p [create_bd_port -dir I adc_clk_p]
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set adc_clk_n [create_bd_port -dir I adc_clk_n]
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set adc_data_p [create_bd_port -dir I -from 11 -to 0 adc_data_p]
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set adc_data_n [create_bd_port -dir I -from 11 -to 0 adc_data_n]
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set adc_or_p [create_bd_port -dir I adc_or_p]
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set adc_or_n [create_bd_port -dir I adc_or_n]
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# spi interface
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set spi_clk_i [create_bd_port -dir I spi_clk_i]
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set spi_clk_o [create_bd_port -dir O spi_clk_o]
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set spi_csn_i [create_bd_port -dir I spi_csn_i]
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set spi_csn_adc_o [create_bd_port -dir O spi_csn_adc_o]
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set spi_csn_clk_o [create_bd_port -dir O spi_csn_clk_o]
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set spi_mosi_i [create_bd_port -dir I spi_mosi_i]
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set spi_mosi_o [create_bd_port -dir O spi_mosi_o]
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set spi_miso_i [create_bd_port -dir I spi_miso_i]
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# interrupts
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set ad9434_dma_intr [create_bd_port -dir O ad9434_dma_intr]
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create_bd_port -dir I adc_clk_p
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create_bd_port -dir I adc_clk_n
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create_bd_port -dir I -from 11 -to 0 adc_data_p
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create_bd_port -dir I -from 11 -to 0 adc_data_n
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create_bd_port -dir I adc_or_p
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create_bd_port -dir I adc_or_n
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# ad9434
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@ -40,90 +26,37 @@ set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9434_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9434_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9434_dma
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# dma interconnect
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set axi_ad9434_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9434_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9434_dma_interconnect
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# additions to default configuration
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set_property -dict [list CONFIG.NUM_MI {9}] $axi_cpu_interconnect
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {15}] $sys_ps7
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set_property LEFT 14 [get_bd_ports GPIO_I]
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set_property LEFT 14 [get_bd_ports GPIO_O]
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set_property LEFT 14 [get_bd_ports GPIO_T]
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# spi connections
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
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connect_bd_net -net spi_csn_adc_o [get_bd_ports spi_csn_adc_o] [get_bd_pins sys_ps7/SPI0_SS_O]
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connect_bd_net -net spi_csn_clk_o [get_bd_ports spi_csn_clk_o] [get_bd_pins sys_ps7/SPI0_SS1_O]
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connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
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connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
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connect_bd_net -net spi_mosi_i [get_bd_ports spi_mosi_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
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connect_bd_net -net spi_mosi_o [get_bd_ports spi_mosi_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
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connect_bd_net -net spi_miso_i [get_bd_ports spi_miso_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
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# ad9434 connections
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9434/delay_clk]
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connect_bd_net -net axi_ad9434_clk [get_bd_pins axi_ad9434/adc_clk]
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connect_bd_net -net axi_ad9434_clk [get_bd_pins axi_ad9434_dma/fifo_wr_clk]
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ad_connect sys_200m_clk axi_ad9434/delay_clk
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ad_connect axi_ad9434/adc_clk axi_ad9434_dma/fifo_wr_clk
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connect_bd_net -net axi_ad9434_clk_in_p [get_bd_ports adc_clk_p] [get_bd_pins axi_ad9434/adc_clk_in_p]
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connect_bd_net -net axi_ad9434_clk_in_n [get_bd_ports adc_clk_n] [get_bd_pins axi_ad9434/adc_clk_in_n]
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connect_bd_net -net axi_ad9434_data_in_p [get_bd_ports adc_data_p] [get_bd_pins axi_ad9434/adc_data_in_p]
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connect_bd_net -net axi_ad9434_data_in_n [get_bd_ports adc_data_n] [get_bd_pins axi_ad9434/adc_data_in_n]
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connect_bd_net -net axi_ad9434_or_in_p [get_bd_ports adc_or_p] [get_bd_pins axi_ad9434/adc_or_in_p]
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connect_bd_net -net axi_ad9434_or_in_n [get_bd_ports adc_or_n] [get_bd_pins axi_ad9434/adc_or_in_n]
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ad_connect adc_clk_p axi_ad9434/adc_clk_in_p
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ad_connect adc_clk_n axi_ad9434/adc_clk_in_n
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ad_connect adc_data_p axi_ad9434/adc_data_in_p
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ad_connect adc_data_n axi_ad9434/adc_data_in_n
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ad_connect adc_or_p axi_ad9434/adc_or_in_p
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ad_connect adc_or_n axi_ad9434/adc_or_in_n
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connect_bd_net -net axi_ad9434_denable [get_bd_pins axi_ad9434/adc_valid] [get_bd_pins axi_ad9434_dma/fifo_wr_en]
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connect_bd_net -net axi_ad9434_data [get_bd_pins axi_ad9434/adc_data] [get_bd_pins axi_ad9434_dma/fifo_wr_din]
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connect_bd_net -net axi_ad9434_ovf [get_bd_pins axi_ad9434/adc_dovf] [get_bd_pins axi_ad9434_dma/fifo_wr_overflow]
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ad_connect axi_ad9434/adc_valid axi_ad9434_dma/fifo_wr_en
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ad_connect axi_ad9434/adc_data axi_ad9434_dma/fifo_wr_din
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ad_connect axi_ad9434/adc_dovf axi_ad9434_dma/fifo_wr_overflow
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connect_bd_net -net axi_ad9434_dma_irq [get_bd_pins axi_ad9434_dma/irq] [get_bd_ports ad9434_dma_intr]
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# interconnect
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# cpu interconnect
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9434/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9434_dma/s_axi]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9434/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9434_dma/s_axi_aclk]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma/s_axi_aresetn]
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ad_cpu_interconnect 0x44A00000 axi_ad9434
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ad_cpu_interconnect 0x44A30000 axi_ad9434_dma
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# memory inteconnect
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set dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
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connect_bd_net -net dma_clk $dma_clk_source
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_cpu_clk axi_ad9434_dma/m_dest_axi
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connect_bd_intf_net -intf_net axi_ad9434_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9434_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9434_dma/m_dest_axi]
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connect_bd_intf_net -intf_net axi_ad9434_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9434_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
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connect_bd_net -net dma_clk [get_bd_pins axi_ad9434_dma_interconnect/ACLK] $dma_clk_source
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connect_bd_net -net dma_clk [get_bd_pins axi_ad9434_dma_interconnect/M00_ACLK] $dma_clk_source
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connect_bd_net -net dma_clk [get_bd_pins axi_ad9434_dma_interconnect/S00_ACLK] $dma_clk_source
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connect_bd_net -net dma_clk [get_bd_pins axi_ad9434_dma/m_dest_axi_aclk]
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connect_bd_net -net dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma_interconnect/ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
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# interrupts
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# address map
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create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9434/s_axi/axi_lite] SEG_data_ad9434_core
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create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9434_dma/s_axi/axi_lite] SEG_data_ad9434_dma
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create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9434_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
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ad_cpu_interrupt ps-13 mb-12 axi_ad9434_dma/irq
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@ -1,6 +1,7 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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set project_name ad9434_fmc_zc706
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@ -9,6 +10,7 @@ adi_project_create $project_name
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adi_project_files $project_name [list "../common/ad9434_spi.v" \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
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adi_project_run $project_name
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@ -41,28 +41,28 @@
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module system_top (
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DDR_addr,
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DDR_ba,
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DDR_cas_n,
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DDR_ck_n,
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DDR_ck_p,
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DDR_cke,
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DDR_cs_n,
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DDR_dm,
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DDR_dq,
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DDR_dqs_n,
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DDR_dqs_p,
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DDR_odt,
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DDR_ras_n,
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DDR_reset_n,
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DDR_we_n,
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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FIXED_IO_ddr_vrn,
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FIXED_IO_ddr_vrp,
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FIXED_IO_mio,
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FIXED_IO_ps_clk,
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FIXED_IO_ps_porb,
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FIXED_IO_ps_srstb,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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gpio_bd,
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@ -89,28 +89,28 @@ module system_top (
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spi_sclk,
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spi_dio);
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inout [14:0] DDR_addr;
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inout [ 2:0] DDR_ba;
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inout DDR_cas_n;
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inout DDR_ck_n;
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inout DDR_ck_p;
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inout DDR_cke;
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inout DDR_cs_n;
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inout [ 3:0] DDR_dm;
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inout [31:0] DDR_dq;
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inout [ 3:0] DDR_dqs_n;
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inout [ 3:0] DDR_dqs_p;
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inout DDR_odt;
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inout DDR_ras_n;
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inout DDR_reset_n;
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inout DDR_we_n;
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inout [14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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inout ddr_cas_n;
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inout ddr_ck_n;
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inout ddr_ck_p;
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inout ddr_cke;
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inout ddr_cs_n;
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inout [ 3:0] ddr_dm;
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inout [31:0] ddr_dq;
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inout [ 3:0] ddr_dqs_n;
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inout [ 3:0] ddr_dqs_p;
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inout ddr_odt;
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inout ddr_ras_n;
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inout ddr_reset_n;
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inout ddr_we_n;
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inout FIXED_IO_ddr_vrn;
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inout FIXED_IO_ddr_vrp;
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inout [53:0] FIXED_IO_mio;
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inout FIXED_IO_ps_clk;
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inout FIXED_IO_ps_porb;
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inout FIXED_IO_ps_srstb;
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inout fixed_io_ddr_vrn;
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inout fixed_io_ddr_vrp;
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inout [53:0] fixed_io_mio;
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inout fixed_io_ps_clk;
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inout fixed_io_ps_porb;
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inout fixed_io_ps_srstb;
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inout [14:0] gpio_bd;
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@ -139,29 +139,22 @@ module system_top (
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// internal signals
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wire [14:0] gpio_i;
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wire [14:0] gpio_o;
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wire [14:0] gpio_t;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire spi_miso;
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wire spi_mosi;
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wire spi_csn_adc;
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wire spi_csn_clk;
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wire [15:0] ps_intrs;
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// instantiations
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genvar n;
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generate
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for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd
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IOBUF i_iobuf_gpio_bd (
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.I (gpio_o[n]),
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.O (gpio_i[n]),
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.T (gpio_t[n]),
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.IO (gpio_bd[n]));
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end
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endgenerate
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ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_gpio (
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.di (gpio_o[14:0]),
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.do (gpio_i[14:0]),
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.dt (gpio_t[14:0]),
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.dio (gpio_bd));
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ad9434_spi i_spi (
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.spi_csn({spi_csn_clk, spi_csn_adc}),
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@ -172,30 +165,30 @@ module system_top (
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);
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system_wrapper i_system_wrapper (
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.DDR_addr (DDR_addr),
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.DDR_ba (DDR_ba),
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.DDR_cas_n (DDR_cas_n),
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.DDR_ck_n (DDR_ck_n),
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.DDR_ck_p (DDR_ck_p),
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.DDR_cke (DDR_cke),
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.DDR_cs_n (DDR_cs_n),
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.DDR_dm (DDR_dm),
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.DDR_dq (DDR_dq),
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.DDR_dqs_n (DDR_dqs_n),
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.DDR_dqs_p (DDR_dqs_p),
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.DDR_odt (DDR_odt),
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.DDR_ras_n (DDR_ras_n),
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.DDR_reset_n (DDR_reset_n),
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.DDR_we_n (DDR_we_n),
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.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
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.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
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.FIXED_IO_mio (FIXED_IO_mio),
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.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
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.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
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.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
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.GPIO_I (gpio_i),
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.GPIO_O (gpio_o),
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||||
.GPIO_T (gpio_t),
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
|
|
@ -203,21 +196,19 @@ module system_top (
|
|||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.ps_intr_0 (ps_intrs[0]),
|
||||
.ps_intr_1 (ps_intrs[1]),
|
||||
.ps_intr_2 (ps_intrs[2]),
|
||||
.ps_intr_3 (ps_intrs[3]),
|
||||
.ps_intr_4 (ps_intrs[4]),
|
||||
.ps_intr_5 (ps_intrs[5]),
|
||||
.ps_intr_6 (ps_intrs[6]),
|
||||
.ps_intr_7 (ps_intrs[7]),
|
||||
.ps_intr_8 (ps_intrs[8]),
|
||||
.ps_intr_9 (ps_intrs[9]),
|
||||
.ps_intr_10 (ps_intrs[10]),
|
||||
.ps_intr_11 (ps_intrs[11]),
|
||||
.ps_intr_12 (ps_intrs[12]),
|
||||
.ps_intr_13 (ps_intrs[13]),
|
||||
.ad9434_dma_intr (ps_intrs[13]),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
.ps_intr_03 (1'b0),
|
||||
.ps_intr_04 (1'b0),
|
||||
.ps_intr_05 (1'b0),
|
||||
.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.ps_intr_11 (1'b0),
|
||||
.ps_intr_12 (1'b0),
|
||||
.spdif (spdif),
|
||||
.adc_clk_p(adc_clk_p),
|
||||
.adc_clk_n(adc_clk_n),
|
||||
|
|
@ -225,14 +216,15 @@ module system_top (
|
|||
.adc_data_n(adc_data_n),
|
||||
.adc_or_p(adc_or_p),
|
||||
.adc_or_n(adc_or_n),
|
||||
.spi_clk_i(1'b0),
|
||||
.spi_clk_o(spi_sclk),
|
||||
.spi_csn_i(1'b1),
|
||||
.spi_csn_adc_o(spi_csn_adc),
|
||||
.spi_csn_clk_o(spi_csn_clk),
|
||||
.spi_mosi_i(spi_mosi),
|
||||
.spi_mosi_o(spi_mosi),
|
||||
.spi_miso_i(spi_miso));
|
||||
.spi0_clk_i (1'b0),
|
||||
.spi0_clk_o (spi_clk),
|
||||
.spi0_csn_0_o (spi_csn_adc),
|
||||
.spi0_csn_1_o (spi_csn_clk),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (spi_miso),
|
||||
.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (spi_mosi));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue