From 845c369c6b1e70a68b37110e88b44be4b7dee94c Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 20 Mar 2019 17:02:23 +0000 Subject: [PATCH] axi_adcvr: Add initial value for reg port definition --- library/xilinx/axi_adxcvr/axi_adxcvr_up.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v index d78fcc524..4a2944805 100644 --- a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v @@ -87,7 +87,6 @@ module axi_adxcvr_up #( output [ 7:0] up_es_sel, output up_es_req, - output reg [15:0] up_es_reset, input up_es_ack, output [ 4:0] up_es_pscale, output [ 1:0] up_es_vrange, @@ -99,6 +98,7 @@ module axi_adxcvr_up #( output [11:0] up_es_hstep, output [31:0] up_es_saddr, input up_es_status, + output reg [15:0] up_es_reset = 'h0, // status