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axi_adcvr: Add initial value for reg port definition

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Istvan Csomortani 2019-03-20 17:02:23 +00:00 committed by István Csomortáni
parent 8996044978
commit 845c369c6b
1 changed files with 1 additions and 1 deletions
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library/xilinx/axi_adxcvr/axi_adxcvr_up.v
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@ -87,7 +87,6 @@ module axi_adxcvr_up #(
output [ 7:0] up_es_sel, output [ 7:0] up_es_sel,
output up_es_req, output up_es_req,
output reg [15:0] up_es_reset,
input up_es_ack, input up_es_ack,
output [ 4:0] up_es_pscale, output [ 4:0] up_es_pscale,
output [ 1:0] up_es_vrange, output [ 1:0] up_es_vrange,
@ -99,6 +98,7 @@ module axi_adxcvr_up #(
output [11:0] up_es_hstep, output [11:0] up_es_hstep,
output [31:0] up_es_saddr, output [31:0] up_es_saddr,
input up_es_status, input up_es_status,
output reg [15:0] up_es_reset = 'h0,
// status // status