axi_ad6676: Update the core, sof interface added
Istvan Csomortani
parent
3cc416ca60
commit
8493bd4329
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@ -16,6 +16,7 @@ M_DEPS += ../common/up_xfer_status.v
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M_DEPS += ../common/up_clock_mon.v
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M_DEPS += ../common/up_adc_common.v
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M_DEPS += ../common/up_adc_channel.v
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M_DEPS += ../common/ad_xcvr_rx_if.v
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M_DEPS += ../common/ad_axi_ip_constr.xdc
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M_DEPS += axi_ad6676_pnmon.v
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M_DEPS += axi_ad6676_channel.v
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@ -45,18 +45,21 @@ module axi_ad6676 (
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// rx_clk is (line-rate/40)
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rx_clk,
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rx_sof,
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rx_valid,
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rx_ready,
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rx_data,
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// dma interface
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adc_clk,
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adc_rst,
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adc_valid_a,
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adc_enable_a,
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adc_data_a,
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adc_valid_b,
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adc_enable_b,
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adc_data_b,
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adc_valid_0,
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adc_enable_0,
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adc_data_0,
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adc_valid_1,
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adc_enable_1,
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adc_data_1,
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adc_dovf,
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adc_dunf,
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@ -92,18 +95,21 @@ module axi_ad6676 (
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// rx_clk is (line-rate/40)
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input rx_clk;
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input [ 3:0] rx_sof;
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input rx_valid;
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output rx_ready;
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input [63:0] rx_data;
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// dma interface
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output adc_clk;
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output adc_rst;
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output adc_valid_a;
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output adc_enable_a;
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output [31:0] adc_data_a;
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output adc_valid_b;
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output adc_enable_b;
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output [31:0] adc_data_b;
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output adc_valid_0;
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output adc_enable_0;
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output [31:0] adc_data_0;
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output adc_valid_1;
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output adc_enable_1;
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output [31:0] adc_data_1;
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input adc_dovf;
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input adc_dunf;
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@ -149,8 +155,8 @@ module axi_ad6676 (
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// internal signals
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wire [31:0] adc_data_a_s;
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wire [31:0] adc_data_b_s;
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wire [31:0] adc_data_0_s;
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wire [31:0] adc_data_1_s;
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wire adc_or_a_s;
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wire adc_or_b_s;
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wire adc_status_s;
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@ -171,6 +177,8 @@ module axi_ad6676 (
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign rx_ready = 1'b1;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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@ -193,18 +201,19 @@ module axi_ad6676 (
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// adc valid
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assign adc_valid_a = 1'b1;
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assign adc_valid_b = 1'b1;
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assign adc_valid_0 = 1'b1;
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assign adc_valid_1 = 1'b1;
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// main (device interface)
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axi_ad6676_if i_if (
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axi_ad6676_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
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.rx_clk (rx_clk),
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.rx_sof (rx_sof),
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.rx_data (rx_data),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data_a (adc_data_a_s),
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.adc_data_b (adc_data_b_s),
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.adc_data_a (adc_data_0_s),
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.adc_data_b (adc_data_1_s),
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.adc_or_a (adc_or_a_s),
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.adc_or_b (adc_or_b_s),
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.adc_status (adc_status_s));
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@ -214,10 +223,10 @@ module axi_ad6676 (
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axi_ad6676_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data (adc_data_a_s),
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.adc_data (adc_data_0_s),
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.adc_or (adc_or_a_s),
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.adc_dfmt_data (adc_data_a),
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.adc_enable (adc_enable_a),
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.adc_dfmt_data (adc_data_0),
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.adc_enable (adc_enable_0),
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.up_adc_pn_err (up_status_pn_err_s[0]),
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.up_adc_pn_oos (up_status_pn_oos_s[0]),
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.up_adc_or (up_status_or_s[0]),
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@ -237,10 +246,10 @@ module axi_ad6676 (
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axi_ad6676_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data (adc_data_b_s),
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.adc_data (adc_data_1_s),
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.adc_or (adc_or_b_s),
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.adc_dfmt_data (adc_data_b),
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.adc_enable (adc_enable_b),
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.adc_dfmt_data (adc_data_1),
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.adc_enable (adc_enable_1),
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.up_adc_pn_err (up_status_pn_err_s[1]),
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.up_adc_pn_oos (up_status_pn_oos_s[1]),
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.up_adc_or (up_status_or_s[1]),
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@ -1,9 +1,9 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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//
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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@ -21,16 +21,16 @@
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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@ -41,10 +41,11 @@
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module axi_ad6676_if (
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// jesd interface
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// jesd interface
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// rx_clk is (line-rate/40)
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rx_clk,
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rx_sof,
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rx_data,
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// adc data output
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@ -57,10 +58,14 @@ module axi_ad6676_if (
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adc_or_b,
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adc_status);
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// jesd interface
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// rx_clk is (line-rate/40)
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// parameters
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parameter DEVICE_TYPE = 0;
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// jesd interface
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input rx_clk;
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input [ 3:0] rx_sof;
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input [63:0] rx_data;
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// adc data output
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@ -83,6 +88,7 @@ module axi_ad6676_if (
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wire [15:0] adc_data_a_s0_s;
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wire [15:0] adc_data_b_s1_s;
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wire [15:0] adc_data_b_s0_s;
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wire [63:0] rx_data_s;
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// adc clock is the reference clock
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@ -99,7 +105,7 @@ module axi_ad6676_if (
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assign adc_data_a_s1_s = {rx_data[23:16], rx_data[31:24]};
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assign adc_data_a_s0_s = {rx_data[ 7: 0], rx_data[15: 8]};
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assign adc_data_b_s1_s = {rx_data[55:48], rx_data[63:56]};
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assign adc_data_b_s1_s = {rx_data[55:48], rx_data[63:56]};
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assign adc_data_b_s0_s = {rx_data[39:32], rx_data[47:40]};
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// status
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@ -112,6 +118,21 @@ module axi_ad6676_if (
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end
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end
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// frame-alignment
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genvar n;
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generate
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for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if
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ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (
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.rx_clk (rx_clk),
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.rx_ip_sof (rx_sof),
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.rx_ip_data (rx_data[((n*32)+31):(n*32)]),
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.rx_sof (),
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.rx_data (rx_data_s[((n*32)+31):(n*32)]));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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@ -13,6 +13,7 @@ adi_ip_files axi_ad6676 [list \
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"$ad_hdl_dir/library/common/up_clock_mon.v" \
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"$ad_hdl_dir/library/common/up_adc_common.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
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"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
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"axi_ad6676_pnmon.v" \
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"axi_ad6676_channel.v" \
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@ -25,6 +26,7 @@ adi_ip_constraints axi_ad6676 [list \
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"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
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"axi_ad6676_constr.xdc" ]
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set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
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