diff --git a/library/axi_ad6676/Makefile b/library/axi_ad6676/Makefile index 07bef5ad4..7e7660720 100644 --- a/library/axi_ad6676/Makefile +++ b/library/axi_ad6676/Makefile @@ -16,6 +16,7 @@ M_DEPS += ../common/up_xfer_status.v M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/ad_xcvr_rx_if.v M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += axi_ad6676_pnmon.v M_DEPS += axi_ad6676_channel.v diff --git a/library/axi_ad6676/axi_ad6676.v b/library/axi_ad6676/axi_ad6676.v index de5b289da..4de586635 100755 --- a/library/axi_ad6676/axi_ad6676.v +++ b/library/axi_ad6676/axi_ad6676.v @@ -45,18 +45,21 @@ module axi_ad6676 ( // rx_clk is (line-rate/40) rx_clk, + rx_sof, + rx_valid, + rx_ready, rx_data, // dma interface adc_clk, adc_rst, - adc_valid_a, - adc_enable_a, - adc_data_a, - adc_valid_b, - adc_enable_b, - adc_data_b, + adc_valid_0, + adc_enable_0, + adc_data_0, + adc_valid_1, + adc_enable_1, + adc_data_1, adc_dovf, adc_dunf, @@ -92,18 +95,21 @@ module axi_ad6676 ( // rx_clk is (line-rate/40) input rx_clk; + input [ 3:0] rx_sof; + input rx_valid; + output rx_ready; input [63:0] rx_data; // dma interface output adc_clk; output adc_rst; - output adc_valid_a; - output adc_enable_a; - output [31:0] adc_data_a; - output adc_valid_b; - output adc_enable_b; - output [31:0] adc_data_b; + output adc_valid_0; + output adc_enable_0; + output [31:0] adc_data_0; + output adc_valid_1; + output adc_enable_1; + output [31:0] adc_data_1; input adc_dovf; input adc_dunf; @@ -149,8 +155,8 @@ module axi_ad6676 ( // internal signals - wire [31:0] adc_data_a_s; - wire [31:0] adc_data_b_s; + wire [31:0] adc_data_0_s; + wire [31:0] adc_data_1_s; wire adc_or_a_s; wire adc_or_b_s; wire adc_status_s; @@ -171,6 +177,8 @@ module axi_ad6676 ( assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; + assign rx_ready = 1'b1; + // processor read interface always @(negedge up_rstn or posedge up_clk) begin @@ -193,18 +201,19 @@ module axi_ad6676 ( // adc valid - assign adc_valid_a = 1'b1; - assign adc_valid_b = 1'b1; + assign adc_valid_0 = 1'b1; + assign adc_valid_1 = 1'b1; // main (device interface) - axi_ad6676_if i_if ( + axi_ad6676_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if ( .rx_clk (rx_clk), + .rx_sof (rx_sof), .rx_data (rx_data), .adc_clk (adc_clk), .adc_rst (adc_rst), - .adc_data_a (adc_data_a_s), - .adc_data_b (adc_data_b_s), + .adc_data_a (adc_data_0_s), + .adc_data_b (adc_data_1_s), .adc_or_a (adc_or_a_s), .adc_or_b (adc_or_b_s), .adc_status (adc_status_s)); @@ -214,10 +223,10 @@ module axi_ad6676 ( axi_ad6676_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), - .adc_data (adc_data_a_s), + .adc_data (adc_data_0_s), .adc_or (adc_or_a_s), - .adc_dfmt_data (adc_data_a), - .adc_enable (adc_enable_a), + .adc_dfmt_data (adc_data_0), + .adc_enable (adc_enable_0), .up_adc_pn_err (up_status_pn_err_s[0]), .up_adc_pn_oos (up_status_pn_oos_s[0]), .up_adc_or (up_status_or_s[0]), @@ -237,10 +246,10 @@ module axi_ad6676 ( axi_ad6676_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), - .adc_data (adc_data_b_s), + .adc_data (adc_data_1_s), .adc_or (adc_or_b_s), - .adc_dfmt_data (adc_data_b), - .adc_enable (adc_enable_b), + .adc_dfmt_data (adc_data_1), + .adc_enable (adc_enable_1), .up_adc_pn_err (up_status_pn_err_s[1]), .up_adc_pn_oos (up_status_pn_oos_s[1]), .up_adc_or (up_status_or_s[1]), diff --git a/library/axi_ad6676/axi_ad6676_if.v b/library/axi_ad6676/axi_ad6676_if.v index b0ddedbb1..ecd68a454 100755 --- a/library/axi_ad6676/axi_ad6676_if.v +++ b/library/axi_ad6676/axi_ad6676_if.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -41,10 +41,11 @@ module axi_ad6676_if ( - // jesd interface + // jesd interface // rx_clk is (line-rate/40) rx_clk, + rx_sof, rx_data, // adc data output @@ -57,10 +58,14 @@ module axi_ad6676_if ( adc_or_b, adc_status); - // jesd interface - // rx_clk is (line-rate/40) + // parameters + + parameter DEVICE_TYPE = 0; + + // jesd interface input rx_clk; + input [ 3:0] rx_sof; input [63:0] rx_data; // adc data output @@ -83,6 +88,7 @@ module axi_ad6676_if ( wire [15:0] adc_data_a_s0_s; wire [15:0] adc_data_b_s1_s; wire [15:0] adc_data_b_s0_s; + wire [63:0] rx_data_s; // adc clock is the reference clock @@ -99,7 +105,7 @@ module axi_ad6676_if ( assign adc_data_a_s1_s = {rx_data[23:16], rx_data[31:24]}; assign adc_data_a_s0_s = {rx_data[ 7: 0], rx_data[15: 8]}; - assign adc_data_b_s1_s = {rx_data[55:48], rx_data[63:56]}; + assign adc_data_b_s1_s = {rx_data[55:48], rx_data[63:56]}; assign adc_data_b_s0_s = {rx_data[39:32], rx_data[47:40]}; // status @@ -112,6 +118,21 @@ module axi_ad6676_if ( end end + // frame-alignment + + genvar n; + + generate + for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if + ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if ( + .rx_clk (rx_clk), + .rx_ip_sof (rx_sof), + .rx_ip_data (rx_data[((n*32)+31):(n*32)]), + .rx_sof (), + .rx_data (rx_data_s[((n*32)+31):(n*32)])); + end + endgenerate + endmodule // *************************************************************************** diff --git a/library/axi_ad6676/axi_ad6676_ip.tcl b/library/axi_ad6676/axi_ad6676_ip.tcl index 3480d7115..ec91fcdc6 100644 --- a/library/axi_ad6676/axi_ad6676_ip.tcl +++ b/library/axi_ad6676/axi_ad6676_ip.tcl @@ -13,6 +13,7 @@ adi_ip_files axi_ad6676 [list \ "$ad_hdl_dir/library/common/up_clock_mon.v" \ "$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "axi_ad6676_pnmon.v" \ "axi_ad6676_channel.v" \ @@ -25,6 +26,7 @@ adi_ip_constraints axi_ad6676 [list \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "axi_ad6676_constr.xdc" ] +set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]