gtlb- up-sync make w1c
Rejeesh Kutty
parent
f1d416a98b
commit
84ced344d9
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@ -39,219 +39,124 @@
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module util_gtlb (
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// receive interface
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rx_clk,
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rx_rst,
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rx_commaalign,
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rx_charisk,
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rx_disperr,
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rx_notintable,
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rx_data,
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// transmit interface
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tx_clk,
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tx_rst,
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tx_charisk,
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tx_data,
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// up interface
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up_clk,
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up_rstn,
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up_rx_sync,
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up_rx_pn_err,
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up_rx_pn_oos);
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// pll clocks & resets
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input qpll_ref_clk,
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input cpll_ref_clk,
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input qpll_ref_clk,
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input cpll_ref_clk,
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output qpll0_rst,
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output qpll0_ref_clk_in,
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output qpll0_rst,
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output qpll0_ref_clk_in,
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input pll_rst_0,
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output cpll_rst_m_0,
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output cpll_ref_clk_in_0,
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input pll_rst_0,
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output cpll_rst_m_0,
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output cpll_ref_clk_in_0,
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// channel interface (rx)
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input rx_p,
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input rx_n,
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input rx_p,
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input rx_n,
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input [ 3:0] rx_gt_charisk;
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input [ 3:0] rx_gt_disperr;
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input [ 3:0] rx_gt_notintable;
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input [31:0] rx_gt_data;
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input [ 3:0] rx_gt_charisk_0,
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input [ 3:0] rx_gt_disperr_0,
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input [ 3:0] rx_gt_notintable_0,
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input [31:0] rx_gt_data_0,
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output reg rx_gt_comma_align_enb_0,
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output rx_out_clk,
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input rx_clk,
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output rx_rst,
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output rx_sof,
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output [((RX_NUM_OF_LANES*32)-1):0] rx_data,
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output rx_ip_rst,
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output rx_ip_rst_done,
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output rx_ip_sysref,
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input rx_ip_sync,
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input [ 3:0] rx_ip_sof,
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input [((RX_NUM_OF_LANES*32)-1):0] rx_ip_data,
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output rx_0_p,
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output rx_0_n,
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input rx_rst_0,
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output rx_rst_m_0,
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input rx_gt_rst_0,
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output rx_gt_rst_m_0,
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input rx_pll_locked_0,
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output rx_pll_locked_m_0,
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input rx_user_ready_0,
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output rx_user_ready_m_0,
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input rx_rst_done_0,
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output rx_rst_done_m_0,
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input rx_out_clk_0,
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output rx_clk_0,
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output rx_sysref_0,
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input rx_sync_0,
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input rx_sof_0,
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input [31:0] rx_data_0,
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input rx_ip_rst_0,
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output [ 3:0] rx_ip_sof_0,
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output [31:0] rx_ip_data_0,
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input rx_ip_sysref_0,
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output rx_ip_sync_0,
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input rx_ip_rst_done_0,
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output rx_0_p,
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output rx_0_n,
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input rx_rst_0,
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output rx_rst_m_0,
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input rx_gt_rst_0,
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output rx_gt_rst_m_0,
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input rx_pll_locked_0,
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output rx_pll_locked_m_0,
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input rx_user_ready_0,
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output rx_user_ready_m_0,
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input rx_rst_done_0,
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output rx_rst_done_m_0,
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input rx_out_clk_0,
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output rx_clk_0,
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output rx_sysref_0,
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input rx_sync_0,
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input rx_sof_0,
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input [31:0] rx_data_0,
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input rx_ip_rst_0,
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output [ 3:0] rx_ip_sof_0,
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output [31:0] rx_ip_data_0,
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input rx_ip_sysref_0,
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output rx_ip_sync_0,
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input rx_ip_rst_done_0,
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// channel interface (tx)
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output tx_p,
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output tx_n,
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output tx_p,
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output tx_n,
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output [ 3:0] tx_gt_charisk,
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output [31:0] tx_gt_data,
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output [ 3:0] tx_gt_charisk_0,
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output reg [31:0] tx_gt_data_0,
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input tx_0_p,
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input tx_0_n,
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input tx_rst_0,
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output tx_rst_m_0,
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input tx_gt_rst_0,
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output tx_gt_rst_m_0,
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input tx_pll_locked_0,
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output tx_pll_locked_m_0,
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input tx_user_ready_0,
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output tx_user_ready_m_0,
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input tx_rst_done_0,
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output tx_rst_done_m_0,
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input tx_out_clk_0,
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output tx_clk_0,
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output tx_sysref_0,
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output tx_sync_0,
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output [31:0] tx_data_0,
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input tx_ip_rst_0,
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input [31:0] tx_ip_data_0,
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input tx_ip_sysref_0,
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input tx_ip_sync_0,
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input tx_ip_rst_done_0);
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assign qpll0_rst = pll_rst_0;
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assign qpll0_ref_clk_in = qpll_ref_clk;
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assign cpll_rst_m_0 = pll_rst_0;
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assign cpll_ref_clk_in_0 = cpll_ref_clk;
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assign rx_0_p = rx_p;
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assign rx_0_n = rx_n;
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assign rx_rst_m_0 = rx_rst_0;
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assign rx_gt_rst_m_0 = rx_gt_rst_0;
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assign rx_pll_locked_m_0 = rx_pll_locked_0;
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assign rx_user_ready_m_0 = rx_user_ready_0;
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assign rx_rst_done_m_0 = & rx_rst_done_0;
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assign rx_clk_0 = rx_clk;
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assign rx_sysref_0 = 1'd0;
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assign rx_ip_sof_0 = 4'hf;
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assign rx_ip_data_0 = rx_gt_data_0;
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assign rx_ip_sync_0 = ?;
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assign tx_p = tx_0_p;
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assign tx_n = tx_0_n;
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assign tx_gt_charisk = ?;
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assign tx_gt_data = tx_ip_data_0;
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assign tx_rst_m_0 = tx_rst_0;
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assign tx_gt_rst_m_0 = tx_gt_rst_0;
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assign tx_pll_locked_m_0 = tx_pll_locked_0;
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assign tx_user_ready_m_0 = tx_user_ready_0;
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assign tx_rst_done_m_0 = tx_rst_done_0;
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assign tx_clk_0 = tx_clk;
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assign tx_sysref_0 = 1'd0;
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assign tx_sync_0 = ?;
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assign tx_data_0 = ?;
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// receive interface
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input rx_clk;
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input rx_rst;
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output rx_commaalign;
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input [ 3:0] rx_charisk;
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input [ 3:0] rx_disperr;
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input [ 3:0] rx_notintable;
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input [31:0] rx_data;
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// transmit interface
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input tx_clk;
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input tx_rst;
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output [ 3:0] tx_charisk;
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output [31:0] tx_data;
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input tx_0_p,
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input tx_0_n,
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input tx_rst_0,
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output tx_rst_m_0,
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input tx_gt_rst_0,
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output tx_gt_rst_m_0,
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input tx_pll_locked_0,
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output tx_pll_locked_m_0,
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input tx_user_ready_0,
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output tx_user_ready_m_0,
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input tx_rst_done_0,
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output tx_rst_done_m_0,
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input tx_out_clk_0,
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output tx_clk_0,
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output tx_sysref_0,
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output tx_sync_0,
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output [31:0] tx_data_0,
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input tx_ip_rst_0,
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input [31:0] tx_ip_data_0,
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input tx_ip_sysref_0,
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input tx_ip_sync_0,
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input tx_ip_rst_done_0,
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// up interface
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input up_clk;
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input up_rstn;
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output up_rx_sync;
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output up_rx_pn_err;
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output up_rx_pn_oos;
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input up_clk,
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input up_rstn,
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input up_pn_err_clr,
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input up_pn_oos_clr,
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output reg up_pn_err,
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output reg up_pn_oos);
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// internal registers
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reg tx_sync_m1 = 'd0;
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reg tx_sync_m2 = 'd0;
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reg tx_sync = 'd0;
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reg [31:0] tx_pn_data = 'd0;
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reg tx_charisk_1 = 'd0;
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reg [31:0] tx_data = 'd0;
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reg rx_commaalign = 'd0;
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reg [ 3:0] rx_kcount = 'd0;
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reg rx_sync = 'd0;
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reg [31:0] rx_pn_data = 'd0;
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reg rx_pn_match_d = 'd0;
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reg rx_pn_match_z = 'd0;
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reg rx_pn_err = 'd0;
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reg rx_pn_oos = 'd0;
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reg [ 3:0] rx_pn_oos_count = 'd0;
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reg up_rx_sync_m1 = 'd0;
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reg up_rx_sync_m2 = 'd0;
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reg up_rx_sync = 'd0;
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reg up_rx_pn_err_m1 = 'd0;
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reg up_rx_pn_err_m2 = 'd0;
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reg up_rx_pn_err = 'd0;
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reg up_rx_pn_oos_m1 = 'd0;
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reg up_rx_pn_oos_m2 = 'd0;
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reg up_rx_pn_oos = 'd0;
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reg tx_sync_m1 = 'd0;
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reg tx_sync_m2 = 'd0;
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reg tx_sync = 'd0;
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reg [ 7:0] tx_clk_count = 'd0;
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reg [31:0] tx_pn_data = 'd0;
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reg tx_charisk_1 = 'd0;
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reg [ 3:0] rx_kcount = 'd0;
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reg rx_sync = 'd0;
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reg [31:0] rx_pn_data = 'd0;
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reg rx_pn_match_d = 'd0;
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reg rx_pn_match_z = 'd0;
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reg rx_pn_err = 'd0;
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reg rx_pn_oos = 'd0;
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reg [ 3:0] rx_pn_oos_count = 'd0;
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reg up_pn_err_clr_d = 'd0;
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reg up_pn_oos_clr_d = 'd0;
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// internal signals
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wire [31:0] rx_pn_data_s;
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wire rx_pn_match_d_s;
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wire rx_pn_match_z_s;
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wire rx_pn_match_s;
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wire rx_pn_update_s;
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wire rx_pn_err_s;
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wire [31:0] rx_gt_data_0_s;
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wire [31:0] rx_pn_data_s;
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wire rx_pn_match_d_s;
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wire rx_pn_match_z_s;
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wire rx_pn_match_s;
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wire rx_pn_update_s;
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wire rx_pn_err_s;
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wire up_pn_err_s;
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wire up_pn_oos_s;
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// pn31 function
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@ -295,42 +200,91 @@ module util_gtlb (
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end
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endfunction
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// defaults
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assign qpll0_rst = pll_rst_0;
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assign qpll0_ref_clk_in = qpll_ref_clk;
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assign cpll_rst_m_0 = pll_rst_0;
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assign cpll_ref_clk_in_0 = cpll_ref_clk;
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assign rx_0_p = rx_p;
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assign rx_0_n = rx_n;
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assign rx_rst_m_0 = rx_rst_0;
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assign rx_gt_rst_m_0 = rx_gt_rst_0;
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assign rx_pll_locked_m_0 = rx_pll_locked_0;
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assign rx_user_ready_m_0 = rx_user_ready_0;
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assign rx_rst_done_m_0 = & rx_rst_done_0;
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assign rx_clk_0 = rx_out_clk_0;
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assign rx_sysref_0 = 1'd0;
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assign rx_ip_sof_0 = 4'hf;
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assign rx_ip_data_0 = 32'd0;
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assign rx_ip_sync_0 = rx_sync;
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assign tx_p = tx_0_p;
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assign tx_n = tx_0_n;
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assign tx_rst_m_0 = tx_rst_0;
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assign tx_gt_rst_m_0 = tx_gt_rst_0;
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assign tx_pll_locked_m_0 = tx_pll_locked_0;
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assign tx_user_ready_m_0 = tx_user_ready_0;
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assign tx_rst_done_m_0 = tx_rst_done_0;
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assign tx_clk_0 = tx_out_clk_0;
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assign tx_sysref_0 = 1'd0;
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assign tx_sync_0 = tx_sync;
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assign tx_data_0 = 32'd0;
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// gt loop back
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assign tx_charisk = {4{tx_charisk_1}};
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assign tx_gt_charisk_0 = {4{tx_charisk_1}};
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always @(posedge tx_clk or posedge tx_rst) begin
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if (tx_rst == 1'b1) begin
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always @(posedge tx_out_clk_0 or posedge tx_rst_0) begin
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if (tx_rst_0 == 1'b1) begin
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tx_sync_m1 <= 1'd0;
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tx_sync_m2 <= 1'd0;
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tx_sync <= 1'd0;
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tx_clk_count <= 8'd0;
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tx_pn_data <= 32'hffffffff;
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tx_charisk_1 <= 1'd0;
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tx_data <= 32'd0;
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tx_gt_data_0 <= 32'd0;
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end else begin
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tx_sync_m1 <= rx_sync;
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tx_sync_m2 <= tx_sync_m1;
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tx_sync <= tx_sync_m2;
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tx_pn_data <= pn31(tx_pn_data);
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tx_clk_count <= tx_clk_count + 1'b1;
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if (tx_clk_count == 0) begin
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tx_pn_data <= 32'hffffffff;
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end else begin
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tx_pn_data <= pn31(tx_pn_data);
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end
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if (tx_sync == 1'b1) begin
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tx_charisk_1 <= 1'd0;
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tx_data <= tx_pn_data;
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tx_gt_data_0[31:24] <= tx_pn_data[ 7: 0];
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tx_gt_data_0[23:16] <= tx_pn_data[15: 8];
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tx_gt_data_0[15: 8] <= tx_pn_data[23:16];
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tx_gt_data_0[ 7: 0] <= tx_pn_data[31:24];
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end else begin
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tx_charisk_1 <= 1'd1;
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tx_data <= 32'hbcbcbcbc;
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tx_gt_data_0[31:24] <= 8'hbc;
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tx_gt_data_0[23:16] <= 8'hbc;
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tx_gt_data_0[15: 8] <= 8'hbc;
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tx_gt_data_0[ 7: 0] <= 8'hbc;
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end
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end
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end
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always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst == 1'b1) begin
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rx_commaalign <= 1'd0;
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assign rx_gt_data_0_s[31:24] = rx_gt_data_0[ 7: 0];
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assign rx_gt_data_0_s[23:16] = rx_gt_data_0[15: 8];
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assign rx_gt_data_0_s[15: 8] = rx_gt_data_0[23:16];
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assign rx_gt_data_0_s[ 7: 0] = rx_gt_data_0[31:24];
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always @(posedge rx_out_clk_0 or posedge rx_rst_0) begin
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if (rx_rst_0 == 1'b1) begin
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rx_gt_comma_align_enb_0 <= 1'd0;
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rx_kcount <= 4'd0;
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rx_sync <= 1'd0;
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end else begin
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rx_commaalign <= ~rx_sync;
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if ((rx_disperr == 0) && (rx_notintable == 0)) begin
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if ((rx_charisk == 4'hf) && (rx_data == 32'hbcbcbcbc)) begin
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rx_gt_comma_align_enb_0 <= ~rx_sync;
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if ((rx_gt_disperr_0 == 0) && (rx_gt_notintable_0 == 0)) begin
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if ((rx_gt_charisk_0 == 4'hf) && (rx_gt_data_0_s == 32'hbcbcbcbc)) begin
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rx_kcount <= rx_kcount + 1'b1;
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if (rx_kcount == 4'hf) begin
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rx_sync <= 1'b1;
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@ -346,15 +300,15 @@ module util_gtlb (
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end
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end
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assign rx_pn_data_s = (rx_pn_oos == 1'b1) ? rx_data : rx_pn_data;
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assign rx_pn_match_d_s = (rx_data == rx_pn_data) ? 1'b1 : 1'b0;
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assign rx_pn_match_z_s = (rx_data == 'd0) ? 1'b0 : 1'b1;
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assign rx_pn_data_s = (rx_pn_oos == 1'b1) ? rx_gt_data_0_s : rx_pn_data;
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assign rx_pn_match_d_s = (rx_gt_data_0_s == rx_pn_data) ? 1'b1 : 1'b0;
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assign rx_pn_match_z_s = (rx_gt_data_0_s == 'd0) ? 1'b0 : 1'b1;
|
||||
assign rx_pn_match_s = rx_pn_match_d & rx_pn_match_z;
|
||||
assign rx_pn_update_s = ~(rx_pn_oos ^ rx_pn_match_s);
|
||||
assign rx_pn_err_s = ~(rx_pn_oos | rx_pn_match_s);
|
||||
|
||||
always @(posedge rx_clk or posedge rx_rst) begin
|
||||
if (rx_rst == 1'b1) begin
|
||||
always @(posedge rx_out_clk_0 or posedge rx_rst_0) begin
|
||||
if (rx_rst_0 == 1'b1) begin
|
||||
rx_pn_data <= 32'd0;
|
||||
rx_pn_match_d <= 'd0;
|
||||
rx_pn_match_z <= 'd0;
|
||||
|
|
@ -365,7 +319,7 @@ module util_gtlb (
|
|||
rx_pn_data <= pn31(rx_pn_data_s);
|
||||
rx_pn_match_d <= rx_pn_match_d_s;
|
||||
rx_pn_match_z <= rx_pn_match_z_s;
|
||||
if ((rx_disperr == 0) && (rx_notintable == 0) && (rx_charisk == 0)) begin
|
||||
if ((rx_gt_disperr_0 == 0) && (rx_gt_notintable_0 == 0) && (rx_gt_charisk_0 == 0)) begin
|
||||
rx_pn_err <= rx_pn_err_s;
|
||||
if ((rx_pn_update_s == 1'b1) && (rx_pn_oos_count >= 15)) begin
|
||||
rx_pn_oos <= ~rx_pn_oos;
|
||||
|
|
@ -385,27 +339,35 @@ module util_gtlb (
|
|||
|
||||
// up clock
|
||||
|
||||
up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_data_status ({up_pn_err_s, up_pn_oos_s}),
|
||||
.d_rst (rx_rst_0),
|
||||
.d_clk (rx_out_clk_0),
|
||||
.d_data_status ({rx_pn_err, rx_pn_oos}));
|
||||
|
||||
always @(posedge up_clk or negedge up_rstn) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_rx_sync_m1 <= 'd0;
|
||||
up_rx_sync_m2 <= 'd0;
|
||||
up_rx_sync <= 'd0;
|
||||
up_rx_pn_err_m1 <= 'd0;
|
||||
up_rx_pn_err_m2 <= 'd0;
|
||||
up_rx_pn_err <= 'd0;
|
||||
up_rx_pn_oos_m1 <= 'd0;
|
||||
up_rx_pn_oos_m2 <= 'd0;
|
||||
up_rx_pn_oos <= 'd0;
|
||||
up_pn_err_clr_d <= 'd0;
|
||||
up_pn_oos_clr_d <= 'd0;
|
||||
up_pn_err <= 'd0;
|
||||
up_pn_oos <= 'd0;
|
||||
end else begin
|
||||
up_rx_sync_m1 <= rx_sync;
|
||||
up_rx_sync_m2 <= up_rx_sync_m1;
|
||||
up_rx_sync <= up_rx_sync_m2;
|
||||
up_rx_pn_err_m1 <= rx_pn_err;
|
||||
up_rx_pn_err_m2 <= up_rx_pn_err_m1;
|
||||
up_rx_pn_err <= up_rx_pn_err_m2;
|
||||
up_rx_pn_oos_m1 <= rx_pn_oos;
|
||||
up_rx_pn_oos_m2 <= up_rx_pn_oos_m1;
|
||||
up_rx_pn_oos <= up_rx_pn_oos_m2;
|
||||
up_pn_err_clr_d <= up_pn_err_clr;
|
||||
up_pn_oos_clr_d <= up_pn_oos_clr;
|
||||
if (up_pn_err_s == 1'b1) begin
|
||||
up_pn_err <= 1'b1;
|
||||
end else if ((up_pn_err_clr == 1'b1) &&
|
||||
(up_pn_err_clr_d == 1'b0)) begin
|
||||
up_pn_err <= 1'b0;
|
||||
end
|
||||
if (up_pn_oos_s == 1'b1) begin
|
||||
up_pn_oos <= 1'b1;
|
||||
end else if ((up_pn_oos_clr == 1'b1) &&
|
||||
(up_pn_oos_clr_d == 1'b0)) begin
|
||||
up_pn_oos <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
|
||||
set_false_path -from [get_cells -hier *rx_sync* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier *tx_sync_m1* -filter {primitive_subgroup == flop}]
|
||||
set_false_path -from [get_cells -hier *rx_sync* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier *up_rx_sync_m1* -filter {primitive_subgroup == flop}]
|
||||
set_false_path -from [get_cells -hier *rx_pn_err* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier *up_rx_pn_err_m1* -filter {primitive_subgroup == flop}]
|
||||
set_false_path -from [get_cells -hier *rx_pn_oos* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier *up_rx_pn_oos_m1* -filter {primitive_subgroup == flop}]
|
||||
set_property shreg_extract no [get_cells -hier -filter {name =~ *tx_sync*}]
|
||||
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
|
||||
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *tx_sync_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}]
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
|
|||
|
||||
adi_ip_create util_gtlb
|
||||
adi_ip_files util_gtlb [list \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"util_gtlb_constr.xdc" \
|
||||
"util_gtlb.v" ]
|
||||
|
||||
adi_ip_properties_lite util_gtlb
|
||||
|
|
@ -12,6 +14,79 @@ adi_ip_constraints util_gtlb [list \
|
|||
"util_gtlb_constr.xdc" ]
|
||||
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
|
||||
adi_if_infer_bus ADI:user:if_gt_qpll master gt_qpll_0 [list \
|
||||
"qpll_rst qpll0_rst "\
|
||||
"qpll_ref_clk qpll0_ref_clk_in "]
|
||||
|
||||
for {set n 0} {$n < 1} {incr n} {
|
||||
|
||||
adi_if_infer_bus ADI:user:if_gt_pll master gt_pll_${n} [list \
|
||||
"pll_rst pll_rst_${n} "\
|
||||
"cpll_rst_m cpll_rst_m_${n} "\
|
||||
"cpll_ref_clk_in cpll_ref_clk_in_${n} "]
|
||||
|
||||
adi_if_infer_bus xilinx.com:display_jesd204:jesd204_rx_bus slave gt_rx_ip_${n} [list \
|
||||
"rxcharisk rx_gt_charisk_${n} "\
|
||||
"rxdisperr rx_gt_disperr_${n} "\
|
||||
"rxnotintable rx_gt_notintable_${n} "\
|
||||
"rxdata rx_gt_data_${n} "]
|
||||
|
||||
adi_if_infer_bus ADI:user:if_gt_rx master gt_rx_${n} [list \
|
||||
"rx_p rx_${n}_p "\
|
||||
"rx_n rx_${n}_n "\
|
||||
"rx_rst rx_rst_${n} "\
|
||||
"rx_rst_m rx_rst_m_${n} "\
|
||||
"rx_gt_rst rx_gt_rst_${n} "\
|
||||
"rx_gt_rst_m rx_gt_rst_m_${n} "\
|
||||
"rx_pll_locked rx_pll_locked_${n} "\
|
||||
"rx_pll_locked_m rx_pll_locked_m_${n} "\
|
||||
"rx_user_ready rx_user_ready_${n} "\
|
||||
"rx_user_ready_m rx_user_ready_m_${n} "\
|
||||
"rx_rst_done rx_rst_done_${n} "\
|
||||
"rx_rst_done_m rx_rst_done_m_${n} "\
|
||||
"rx_out_clk rx_out_clk_${n} "\
|
||||
"rx_clk rx_clk_${n} "\
|
||||
"rx_sysref rx_sysref_${n} "\
|
||||
"rx_sync rx_sync_${n} "\
|
||||
"rx_sof rx_sof_${n} "\
|
||||
"rx_data rx_data_${n} "\
|
||||
"rx_ip_rst rx_ip_rst_${n} "\
|
||||
"rx_ip_sof rx_ip_sof_${n} "\
|
||||
"rx_ip_data rx_ip_data_${n} "\
|
||||
"rx_ip_sysref rx_ip_sysref_${n} "\
|
||||
"rx_ip_sync rx_ip_sync_${n} "\
|
||||
"rx_ip_rst_done rx_ip_rst_done_${n} "]
|
||||
|
||||
adi_if_infer_bus xilinx.com:display_jesd204:jesd204_tx_bus master gt_tx_ip_${n} [list \
|
||||
"txcharisk tx_gt_charisk_${n} "\
|
||||
"txdata tx_gt_data_${n} "]
|
||||
|
||||
adi_if_infer_bus ADI:user:if_gt_tx master gt_tx_${n} [list \
|
||||
"tx_p tx_${n}_p "\
|
||||
"tx_n tx_${n}_n "\
|
||||
"tx_rst tx_rst_${n} "\
|
||||
"tx_rst_m tx_rst_m_${n} "\
|
||||
"tx_gt_rst tx_gt_rst_${n} "\
|
||||
"tx_gt_rst_m tx_gt_rst_m_${n} "\
|
||||
"tx_pll_locked tx_pll_locked_${n} "\
|
||||
"tx_pll_locked_m tx_pll_locked_m_${n} "\
|
||||
"tx_user_ready tx_user_ready_${n} "\
|
||||
"tx_user_ready_m tx_user_ready_m_${n} "\
|
||||
"tx_rst_done tx_rst_done_${n} "\
|
||||
"tx_rst_done_m tx_rst_done_m_${n} "\
|
||||
"tx_out_clk tx_out_clk_${n} "\
|
||||
"tx_clk tx_clk_${n} "\
|
||||
"tx_sysref tx_sysref_${n} "\
|
||||
"tx_sync tx_sync_${n} "\
|
||||
"tx_data tx_data_${n} "\
|
||||
"tx_ip_rst tx_ip_rst_${n} "\
|
||||
"tx_ip_data tx_ip_data_${n} "\
|
||||
"tx_ip_sysref tx_ip_sysref_${n} "\
|
||||
"tx_ip_sync tx_ip_sync_${n} "\
|
||||
"tx_ip_rst_done tx_ip_rst_done_${n} "]
|
||||
}
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue