diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v index 1b524ca70..442476e08 100644 --- a/library/axi_ad9671/axi_ad9671.v +++ b/library/axi_ad9671/axi_ad9671.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -45,8 +43,10 @@ module axi_ad9671 ( // rx_clk is (line-rate/40) rx_clk, - rx_data, rx_sof, + rx_valid, + rx_data, + rx_ready, // dma interface @@ -88,14 +88,15 @@ module axi_ad9671 ( parameter ID = 0; parameter DEVICE_TYPE = 0; parameter QUAD_OR_DUAL_N = 1; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; // jesd interface // rx_clk is the jesd clock (ref_clk/2) input rx_clk; - input [(64*QUAD_OR_DUAL_N)+63:0] rx_data; - input rx_sof; + input [ 3:0] rx_sof; + input rx_valid; + input [(64*QUAD_OR_DUAL_N)+63:0] rx_data; + output rx_ready; // dma interface @@ -172,6 +173,7 @@ module axi_ad9671 ( // signal name changes + assign rx_ready = 1'b1; assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; @@ -201,9 +203,10 @@ module axi_ad9671 ( // main (device interface) axi_ad9671_if #( - .QUAD_OR_DUAL_N(QUAD_OR_DUAL_N), - .ID(ID) - ) i_if ( + .QUAD_OR_DUAL_N (QUAD_OR_DUAL_N), + .ID (ID), + .DEVICE_TYPE (DEVICE_TYPE)) + i_if ( .rx_clk (rx_clk), .rx_data (rx_data), .rx_sof (rx_sof), @@ -232,8 +235,8 @@ module axi_ad9671 ( .adc_sync_out (adc_sync_out), .adc_sync_status (adc_sync_status_s), .adc_status (adc_status_s), - .adc_raddr_in(adc_raddr_in), - .adc_raddr_out(adc_raddr_out)); + .adc_raddr_in (adc_raddr_in), + .adc_raddr_out (adc_raddr_out)); // channels @@ -267,9 +270,7 @@ module axi_ad9671 ( // common processor control - up_adc_common #( - .ID(ID) - ) i_up_adc_common ( + up_adc_common #(.ID (ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -310,9 +311,7 @@ module axi_ad9671 ( // up bus interface - up_axi #( - .ADDRESS_WIDTH (14) - ) i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_ad9671/axi_ad9671_hw.tcl b/library/axi_ad9671/axi_ad9671_hw.tcl index 4d03ba575..ea7c1995b 100644 --- a/library/axi_ad9671/axi_ad9671_hw.tcl +++ b/library/axi_ad9671/axi_ad9671_hw.tcl @@ -2,6 +2,7 @@ package require -exact qsys 14.0 source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl set_module_property NAME axi_ad9671 set_module_property DESCRIPTION "AXI AD9671 Interface" @@ -23,11 +24,13 @@ add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v +add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v add_fileset_file axi_ad9671_pnmon.v VERILOG PATH axi_ad9671_pnmon.v add_fileset_file axi_ad9671_if.v VERILOG PATH axi_ad9671_if.v add_fileset_file axi_ad9671_channel.v VERILOG PATH axi_ad9671_channel.v add_fileset_file axi_ad9671.v VERILOG PATH axi_ad9671.v TOP_LEVEL_FILE +add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc # parameters @@ -65,7 +68,7 @@ add_interface s_axi axi4lite end set_interface_property s_axi associatedClock s_axi_clock set_interface_property s_axi associatedReset s_axi_reset add_interface_port s_axi s_axi_awvalid awvalid Input 1 -add_interface_port s_axi s_axi_awaddr awaddr Input 14 +add_interface_port s_axi s_axi_awaddr awaddr Input 16 add_interface_port s_axi s_axi_awprot awprot Input 3 add_interface_port s_axi s_axi_awready awready Output 1 add_interface_port s_axi s_axi_wvalid wvalid Input 1 @@ -76,7 +79,7 @@ add_interface_port s_axi s_axi_bvalid bvalid Output 1 add_interface_port s_axi s_axi_bresp bresp Output 2 add_interface_port s_axi s_axi_bready bready Input 1 add_interface_port s_axi s_axi_arvalid arvalid Input 1 -add_interface_port s_axi s_axi_araddr araddr Input 14 +add_interface_port s_axi s_axi_araddr araddr Input 16 add_interface_port s_axi s_axi_arprot arprot Input 3 add_interface_port s_axi s_axi_arready arready Output 1 add_interface_port s_axi s_axi_rvalid rvalid Output 1 @@ -86,31 +89,36 @@ add_interface_port s_axi s_axi_rready rready Input 1 # transceiver interface -add_interface xcvr_clk clock end -add_interface_port xcvr_clk rx_clk clk Input 1 +ad_alt_intf clock rx_clk input 1 +ad_alt_intf signal rx_sof input 4 export -add_interface xcvr_data conduit end -set_interface_property xcvr_data associatedClock xcvr_clk -add_interface_port xcvr_data rx_data data Input 64*QUAD_OR_DUAL_N+64 -add_interface_port xcvr_data rx_sof data_sof Input 1 +add_interface if_rx_data avalon_streaming sink +add_interface_port if_rx_data rx_data data input 64*QUAD_OR_DUAL_N+64 +add_interface_port if_rx_data rx_valid valid input 1 +add_interface_port if_rx_data rx_ready ready output 1 +set_interface_property if_rx_data associatedClock if_rx_clk +set_interface_property if_rx_data dataBitsPerSymbol 64 -add_interface xcvr_sync conduit end -set_interface_property xcvr_sync associatedClock xcvr_clk -add_interface_port xcvr_sync adc_sync_in sync_in Input 1 -add_interface_port xcvr_sync adc_sync_out sync_out Output 1 -add_interface_port xcvr_sync adc_raddr_in raddr_in Input 4 -add_interface_port xcvr_sync adc_raddr_out raddr_out Output 4 +add_interface if_sync conduit end +set_interface_property if_sync associatedClock if_clk +add_interface_port if_sync adc_sync_in sync_in Input 1 +add_interface_port if_sync adc_sync_out sync_out Output 1 +add_interface_port if_sync adc_raddr_in raddr_in Input 4 +add_interface_port if_sync adc_raddr_out raddr_out Output 4 # dma interface -add_interface adc_clock clock start -add_interface_port adc_clock adc_clk clk Output 1 +ad_alt_intf clock adc_clk output 1 +ad_alt_intf reset adc_rst output 1 if_adc_clk -add_interface adc_dma_if conduit end -set_interface_property adc_dma_if associatedClock adc_clock -add_interface_port adc_dma_if adc_valid valid Output 8 -add_interface_port adc_dma_if adc_enable enable Output 8 -add_interface_port adc_dma_if adc_data data Output 128 -add_interface_port adc_dma_if adc_dovf dovf Input 1 -add_interface_port adc_dma_if adc_dunf dunf Input 1 +add_interface adc_ch conduit end +add_interface_port adc_ch adc_enable enable Output 8 +add_interface_port adc_ch adc_valid valid Output 8 +add_interface_port adc_ch adc_data data Output 128 + +set_interface_property adc_ch associatedClock if_rx_clk +set_interface_property adc_ch associatedReset none + +ad_alt_intf signal adc_dovf input 1 ovf +ad_alt_intf signal adc_dunf input 1 unf diff --git a/library/axi_ad9671/axi_ad9671_if.v b/library/axi_ad9671/axi_ad9671_if.v index 4e838487f..9b8eaabb6 100644 --- a/library/axi_ad9671/axi_ad9671_if.v +++ b/library/axi_ad9671/axi_ad9671_if.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -81,14 +79,15 @@ module axi_ad9671_if ( // parameters parameter QUAD_OR_DUAL_N = 1; + parameter DEVICE_TYPE = 0; parameter ID = 0; // jesd interface // rx_clk is (line-rate/40) input rx_clk; - input rx_sof; - input [(64*QUAD_OR_DUAL_N)+63:0] rx_data; + input [ 3:0] rx_sof; + input [(64*QUAD_OR_DUAL_N)+63:0] rx_data; // adc data output @@ -122,6 +121,8 @@ module axi_ad9671_if ( // internal wires + wire [(2*QUAD_OR_DUAL_N)+1:0] rx_sof_s; + wire [(64*QUAD_OR_DUAL_N)+63:0] rx_data_s; wire [127:0] adc_wdata; wire [127:0] adc_rdata; wire [ 15:0] adc_data_a_s; @@ -142,17 +143,16 @@ module axi_ad9671_if ( reg adc_status = 'd0; reg adc_sync_status = 'd0; reg rx_sof_d = 'd0; - reg [ 3:0] adc_waddr = 'd0; reg [ 3:0] adc_raddr_out = 'd0; - reg [ 15:0] adc_data_a; - reg [ 15:0] adc_data_b; - reg [ 15:0] adc_data_c; - reg [ 15:0] adc_data_d; - reg [ 15:0] adc_data_e; - reg [ 15:0] adc_data_f; - reg [ 15:0] adc_data_g; - reg [ 15:0] adc_data_h; + reg [ 15:0] adc_data_a = 'd0; + reg [ 15:0] adc_data_b = 'd0; + reg [ 15:0] adc_data_c = 'd0; + reg [ 15:0] adc_data_d = 'd0; + reg [ 15:0] adc_data_e = 'd0; + reg [ 15:0] adc_data_f = 'd0; + reg [ 15:0] adc_data_g = 'd0; + reg [ 15:0] adc_data_h = 'd0; // adc clock & valid @@ -219,12 +219,12 @@ module axi_ad9671_if ( always @(posedge rx_clk) begin if (QUAD_OR_DUAL_N == 1'b1) begin int_valid <= 1'b1; - int_data <= rx_data; + int_data <= rx_data_s; end else begin - rx_sof_d <= rx_sof; + rx_sof_d <= &rx_sof_s; int_valid <= rx_sof_d; - int_data[63:0] <= {rx_data[31:0], int_data[63:32]}; - int_data[127:64] <= {rx_data[63:32], int_data[127:96]}; + int_data[63:0] <= {rx_data_s[31: 0], int_data[ 63:32]}; + int_data[127:64] <= {rx_data_s[63:32], int_data[127:96]}; end end @@ -245,6 +245,21 @@ module axi_ad9671_if ( .addrb(adc_raddr_s), .doutb(adc_rdata)); + // frame-alignment + + genvar n; + + generate + for (n = 0; n < ((2*QUAD_OR_DUAL_N)+2); n = n + 1) begin: g_xcvr_if + ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if ( + .rx_clk (rx_clk), + .rx_ip_sof (rx_sof), + .rx_ip_data (rx_data[((n*32)+31):(n*32)]), + .rx_sof (rx_sof_s[n]), + .rx_data (rx_data_s[((n*32)+31):(n*32)])); + end + endgenerate + endmodule // *************************************************************************** diff --git a/library/axi_ad9671/axi_ad9671_ip.tcl b/library/axi_ad9671/axi_ad9671_ip.tcl index a51cccfc9..f7ccf834b 100644 --- a/library/axi_ad9671/axi_ad9671_ip.tcl +++ b/library/axi_ad9671/axi_ad9671_ip.tcl @@ -15,6 +15,7 @@ adi_ip_files axi_ad9671 [list \ "$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \ "$ad_hdl_dir/library/common/ad_mem.v" \ + "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "axi_ad9671_pnmon.v" \ "axi_ad9671_channel.v" \ @@ -28,6 +29,7 @@ adi_ip_constraints axi_ad9671 [list \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "axi_ad9671_constr.xdc" ] +set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]]