diff --git a/projects/adrv9371x/a10gx/system_constr.sdc b/projects/adrv9371x/a10gx/system_constr.sdc
index e7e033307..6c78e9e61 100644
--- a/projects/adrv9371x/a10gx/system_constr.sdc
+++ b/projects/adrv9371x/a10gx/system_constr.sdc
@@ -1,7 +1,7 @@
 
 create_clock -period "10.000 ns"  -name sys_clk_100mhz      [get_ports {sys_clk}]
-create_clock -period  "8.138 ns"  -name ref_clk0            [get_ports {ref_clk0}]
-create_clock -period  "8.138 ns"  -name ref_clk1            [get_ports {ref_clk1}]
+create_clock -period  "8.1300813 ns"  -name ref_clk0            [get_ports {ref_clk0}]
+create_clock -period  "8.1300813 ns"  -name ref_clk1            [get_ports {ref_clk1}]
 
 derive_pll_clocks
 derive_clock_uncertainty
diff --git a/projects/adrv9371x/a10soc/system_constr.sdc b/projects/adrv9371x/a10soc/system_constr.sdc
index 029c5d9b2..d1fa00d63 100644
--- a/projects/adrv9371x/a10soc/system_constr.sdc
+++ b/projects/adrv9371x/a10soc/system_constr.sdc
@@ -1,7 +1,7 @@
 
 create_clock -period "10.000 ns"  -name sys_clk_100mhz      [get_ports {sys_clk}]
-create_clock -period  "8.138 ns"  -name ref_clk0            [get_ports {ref_clk0}]
-create_clock -period  "8.138 ns"  -name ref_clk1            [get_ports {ref_clk1}]
+create_clock -period  "8.1300813 ns"  -name ref_clk0            [get_ports {ref_clk0}]
+create_clock -period  "8.1300813 ns"  -name ref_clk1            [get_ports {ref_clk1}]
 
 derive_pll_clocks
 derive_clock_uncertainty
diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl
index 4707844bd..d34898362 100644
--- a/projects/adrv9371x/common/adrv9371x_qsys.tcl
+++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl
@@ -2,13 +2,17 @@ set dac_fifo_name avl_ad9371_tx_fifo
 set dac_data_width 128
 set dac_dma_data_width 128
 
+# NOTE: The real lane rate is 4915.2 Gbps (Tx/RX/Rx_Obs), with a real reference
+# clock frequency of 122.88 MHz. A round up needed because the fPLL's
+# configuration interface does not support fractional numbers.
+
 # ad9371_tx JESD204
 
 add_instance ad9371_tx_jesd204 adi_jesd204
 set_instance_parameter_value ad9371_tx_jesd204 {ID} {0}
 set_instance_parameter_value ad9371_tx_jesd204 {TX_OR_RX_N} {1}
-set_instance_parameter_value ad9371_tx_jesd204 {LANE_RATE} {4915.2}
-set_instance_parameter_value ad9371_tx_jesd204 {REFCLK_FREQUENCY} {122.88}
+set_instance_parameter_value ad9371_tx_jesd204 {LANE_RATE} {4920}
+set_instance_parameter_value ad9371_tx_jesd204 {REFCLK_FREQUENCY} {123}
 set_instance_parameter_value ad9371_tx_jesd204 {NUM_OF_LANES} {4}
 set_instance_parameter_value ad9371_tx_jesd204 {LANE_MAP} {3 0 1 2}
 set_instance_parameter_value ad9371_tx_jesd204 {SOFT_PCS} {false}
@@ -29,8 +33,8 @@ set_interface_property tx_sync EXPORT_OF ad9371_tx_jesd204.sync
 add_instance ad9371_rx_jesd204 adi_jesd204
 set_instance_parameter_value ad9371_rx_jesd204 {ID} {1}
 set_instance_parameter_value ad9371_rx_jesd204 {TX_OR_RX_N} {0}
-set_instance_parameter_value ad9371_rx_jesd204 {LANE_RATE} {4915.2}
-set_instance_parameter_value ad9371_rx_jesd204 {REFCLK_FREQUENCY} {122.88}
+set_instance_parameter_value ad9371_rx_jesd204 {LANE_RATE} {4920}
+set_instance_parameter_value ad9371_rx_jesd204 {REFCLK_FREQUENCY} {123}
 set_instance_parameter_value ad9371_rx_jesd204 {NUM_OF_LANES} {2}
 set_instance_parameter_value ad9371_rx_jesd204 {SOFT_PCS} {false}
 
@@ -50,8 +54,8 @@ set_interface_property rx_sync EXPORT_OF ad9371_rx_jesd204.sync
 add_instance ad9371_rx_os_jesd204 adi_jesd204
 set_instance_parameter_value ad9371_rx_os_jesd204 {ID} {1}
 set_instance_parameter_value ad9371_rx_os_jesd204 {TX_OR_RX_N} {0}
-set_instance_parameter_value ad9371_rx_os_jesd204 {LANE_RATE} {4915.2}
-set_instance_parameter_value ad9371_rx_os_jesd204 {REFCLK_FREQUENCY} {122.88}
+set_instance_parameter_value ad9371_rx_os_jesd204 {LANE_RATE} {4920}
+set_instance_parameter_value ad9371_rx_os_jesd204 {REFCLK_FREQUENCY} {123}
 set_instance_parameter_value ad9371_rx_os_jesd204 {SOFT_PCS} {false}
 set_instance_parameter_value ad9371_rx_os_jesd204 {NUM_OF_LANES} {2}