library/common/tb/tb_base.v: Update license header
* Removed the commercial JESD license and put the ADIBSD or GPL v2 like for other Verilog files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>main
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
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//
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//
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// The ADI JESD204 Core is released under the following license, which is
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// In this HDL repository, there are many different and unique modules, consisting
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// different than all other HDL cores in this repository.
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// The user should read each of these license terms, and understand the
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// by using this source code/core.
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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// A PARTICULAR PURPOSE.
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//
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//
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// You should have received a copy of the GNU General Public License version 2
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// Redistribution and use of source or resulting binaries, with or without modification
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// along with this source code, and binary. If not, see
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// of this file, are permitted under one of the following two license terms:
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// <http://www.gnu.org/licenses/>.
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//
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// 1. The GNU General Public License version 2 as published by the
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// available under terms different than the General Public License. (e.g. they
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// Free Software Foundation, which can be found in the top level directory
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// of this repository (LICENSE_GPL2), and also online at:
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// core with any corresponding source code.) For these alternate terms you must
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// OR
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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reg clk = 1'b0;
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reg clk = 1'b0;
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reg [3:0] reset_shift = 4'b1111;
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reg [3:0] reset_shift = 4'b1111;
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