Update cn0363 spi engine (#1183)
* Update cn0363 spi engine I replaced the SPI Engine connections in the cn0363_bd.tcl with the spi_engine_create procedure found in the spi_engine.tcl script. Through these changes, a more generic instantiation for the spi_engine can be achieved. I updated the system_constr.xdc file and created the cn0363_pmod.txt file. Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>main
PIoandan
GitHub
parent
b1002cacbe
commit
86216958a7
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@ -2,7 +2,7 @@
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Here are some pointers to help you:
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* [Board Product Page](https://www.analog.com/CN0363)
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* Parts : [24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers](https://www.analog.com/AD7175-2)
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* Parts : [AD7175-2, 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers](https://www.analog.com/AD7175-2)
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* Project Doc: https://wiki.analog.com/resources/eval/user-guides/eval-cn0363-pmdz
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* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/eval-cn0363-pmdz/reference_hdl
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* Linux Drivers: https://wiki.analog.com/resources/eval/user-guides/eval-cn0363-pmdz/software/linux/drivers
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@ -3,6 +3,10 @@
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### SPDX short identifier: ADIBSD
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###############################################################################
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
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proc load_fir_filter_vector {filter_file} {
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set fp [open $filter_file r]
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set data [split [read $fp] "\n"]
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@ -42,64 +46,32 @@ ad_ip_parameter axi_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_ip_parameter axi_dma CONFIG.DMA_AXI_PROTOCOL_DEST 1
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# Create SPI engine controller with offload
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create_bd_cell -type hier spi
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current_bd_instance /spi
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir O conv_done
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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set data_width 8
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set async_spi_clk 0
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set num_cs 2
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set num_sdi 1
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set num_sdo 1
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set sdi_delay 1
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set echo_sclk 0
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ad_ip_instance spi_engine_execution execution
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ad_ip_instance axi_spi_engine axi
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ad_ip_instance spi_engine_offload offload
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_instance util_sigma_delta_spi util_sigma_delta_spi
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set hier_spi_engine spi_cn0363
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ad_ip_parameter execution CONFIG.NUM_OF_CS 2
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ad_ip_parameter util_sigma_delta_spi CONFIG.NUM_OF_CS 2
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ad_ip_parameter interconnect CONFIG.NUM_OF_SDI 2
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ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
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spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
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ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect offload/offload_sdi M_AXIS_SAMPLE
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ad_connect $sys_cpu_clk $hier_spi_engine/clk
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ad_connect sys_cpu_resetn $hier_spi_engine/resetn
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ad_connect util_sigma_delta_spi/data_ready offload/trigger
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ad_connect util_sigma_delta_spi/data_ready conv_done
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ad_ip_instance util_sigma_delta_spi util_sigma_delta_spi
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ad_ip_parameter util_sigma_delta_spi CONFIG.NUM_OF_CS $num_cs
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ad_connect execution/active util_sigma_delta_spi/spi_active
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ad_connect execution/spi util_sigma_delta_spi/s_spi
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ad_connect util_sigma_delta_spi/m_spi m_spi
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ad_connect $hier_spi_engine/clk util_sigma_delta_spi/clk
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ad_connect util_sigma_delta_spi/resetn $hier_spi_engine/resetn
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connect_bd_net \
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[get_bd_pins clk] \
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[get_bd_pins offload/spi_clk] \
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[get_bd_pins offload/ctrl_clk] \
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[get_bd_pins execution/clk] \
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[get_bd_pins axi/s_axi_aclk] \
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[get_bd_pins axi/spi_clk] \
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[get_bd_pins interconnect/clk] \
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[get_bd_pins util_sigma_delta_spi/clk]
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connect_bd_net \
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[get_bd_pins axi/spi_resetn] \
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[get_bd_pins offload/spi_resetn] \
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[get_bd_pins execution/resetn] \
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[get_bd_pins interconnect/resetn] \
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[get_bd_pins util_sigma_delta_spi/resetn]
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connect_bd_net [get_bd_pins resetn] [get_bd_pins axi/s_axi_aresetn]
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ad_connect irq axi/irq
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current_bd_instance /
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
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ad_connect spi/m_spi spi
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ad_connect $hier_spi_engine/m_spi util_sigma_delta_spi/s_spi
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ad_connect util_sigma_delta_spi/data_ready $hier_spi_engine/trigger
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ad_connect $hier_spi_engine/${hier_spi_engine}_execution/active util_sigma_delta_spi/spi_active
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ad_connect util_sigma_delta_spi/m_spi spi
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ad_ip_instance c_counter_binary phase_gen
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ad_ip_instance xlslice phase_slice
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@ -248,9 +220,9 @@ current_bd_instance /processing
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current_bd_instance /
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ad_connect /spi/M_AXIS_SAMPLE /processing/S_AXIS_SAMPLE
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ad_connect /spi/conv_done /processing/conv_done
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ad_connect /processing/S_AXIS_SAMPLE $hier_spi_engine/M_AXIS_SAMPLE
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ad_connect /phase_gen/Q /processing/phase
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ad_connect util_sigma_delta_spi/data_ready /processing/conv_done
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ad_ip_instance axi_generic_adc axi_adc
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ad_ip_parameter axi_adc CONFIG.NUM_OF_CHANNELS 14
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@ -259,7 +231,6 @@ ad_connect processing/overflow axi_adc/adc_dovf
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ad_connect axi_adc/adc_enable processing/channel_enable
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connect_bd_net -net $sys_cpu_clk \
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[get_bd_pins /spi/clk] \
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[get_bd_pins /processing/clk] \
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[get_bd_pins /axi_dma/m_dest_axi_aclk] \
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[get_bd_pins /axi_dma/fifo_wr_clk] \
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@ -267,18 +238,17 @@ connect_bd_net -net $sys_cpu_clk \
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[get_bd_pins /axi_adc/adc_clk]
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connect_bd_net -net $sys_cpu_resetn \
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[get_bd_pins /spi/resetn] \
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[get_bd_pins /processing/resetn] \
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[get_bd_pins /axi_dma/m_dest_axi_aresetn]
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ad_connect /processing/dma_wr /axi_dma/fifo_wr
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ad_cpu_interconnect 0x43c00000 /axi_adc
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ad_cpu_interconnect 0x44a00000 /spi/axi
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ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
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ad_cpu_interconnect 0x44a30000 /axi_dma
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ad_cpu_interrupt "ps-13" "mb-13" /axi_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" /spi/irq
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ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
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ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_cpu_clk axi_dma/m_dest_axi
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@ -0,0 +1,12 @@
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Pin Port Schematic_name System_top_name IOSTANDARD Termination
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# cn0363
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2 PMOD_1 GAIN0 gain0_o LVCMOS33 #N/A
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4 PMOD_2 GAIN1 gain1_o LVCMOS33 #N/A
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8 PMOD_4 EXT_LED_CLK led_clk_o LVCMOS33 #N/A
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6 PMOD_3 DA_CSn spi_cs[1] LVCMOS33 #N/A
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1 PMOD_7 AD_CSn spi_cs[0] LVCMOS33 #N/A
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3 PMOD_8 AD_DIN spi_sdo LVCMOS33 PULLTYPE PULLUP
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5 PMOD_9 AD_DOUT spi_sdi LVCMOS33 PULLTYPE PULLUP
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7 PMOD_10 AD_CLK spi_sclk LVCMOS33 #N/A
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@ -10,6 +10,7 @@ M_DEPS += ../common/cn0363_bd.tcl
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/zed/zed_system_constr.xdc
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M_DEPS += ../../common/zed/zed_system_bd.tcl
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M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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LIB_DEPS += axi_clkgen
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@ -5,23 +5,11 @@
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# PMOD JA
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set_property PACKAGE_PIN Y11 [get_ports gain0_o]
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set_property IOSTANDARD LVCMOS33 [get_ports gain0_o]
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set_property PACKAGE_PIN AA11 [get_ports gain1_o]
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set_property IOSTANDARD LVCMOS33 [get_ports gain1_o]
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set_property PACKAGE_PIN AA9 [get_ports led_clk_o]
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set_property IOSTANDARD LVCMOS33 [get_ports led_clk_o]
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set_property PACKAGE_PIN Y10 [get_ports {spi_cs[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {spi_cs[1]}]
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set_property PACKAGE_PIN AB11 [get_ports {spi_cs[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {spi_cs[0]}]
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set_property PACKAGE_PIN AB10 [get_ports spi_sdo]
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set_property IOSTANDARD LVCMOS33 [get_ports spi_sdo]
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set_property PULLUP true [get_ports spi_sdo]
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set_property PACKAGE_PIN AB9 [get_ports spi_sdi]
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set_property IOSTANDARD LVCMOS33 [get_ports spi_sdi]
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set_property PULLUP true [get_ports spi_sdi]
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set_property PACKAGE_PIN AA8 [get_ports spi_sclk]
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set_property IOSTANDARD LVCMOS33 [get_ports spi_sclk]
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set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports gain0_o] ; ## PMOD JA1
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set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports gain1_o] ; ## PMOD JA2
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set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports led_clk_o] ; ## PMOD JA4
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set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports {spi_cs[1]}] ; ## PMOD JA3
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set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS33} [get_ports {spi_cs[0]}] ; ## PMOD JA7
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set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports spi_sdo] ; ## PMOD JA8
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set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33 PULLUP true} [get_ports spi_sdi] ; ## PMOD JA9
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set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports spi_sclk] ; ## PMOD JA10
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