From 862bd7ef2cc235fa59446d042fab99b9d5e1b618 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 23 Nov 2016 15:02:20 -0500 Subject: [PATCH] daq3/zc706- xcvr changes --- library/axi_ad9152/axi_ad9152_ip.tcl | 1 + projects/daq3/common/daq3_bd.tcl | 54 +++++++++++++++------------- projects/daq3/zc706/system_bd.tcl | 31 +--------------- projects/daq3/zc706/system_top.v | 2 -- 4 files changed, 32 insertions(+), 56 deletions(-) diff --git a/library/axi_ad9152/axi_ad9152_ip.tcl b/library/axi_ad9152/axi_ad9152_ip.tcl index 055b8becb..9fb507c42 100644 --- a/library/axi_ad9152/axi_ad9152_ip.tcl +++ b/library/axi_ad9152/axi_ad9152_ip.tcl @@ -29,6 +29,7 @@ adi_ip_constraints axi_ad9152 [list \ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] ipx::save_core [ipx::current_core] diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index 35ded3e5f..543fc4ea5 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -6,14 +6,16 @@ set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9152_xcvr set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9152_xcvr set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9152_xcvr -set sys_ad9152_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9152_rstgen] - -set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core] - set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9152_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd +set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core] + +set axi_ad9152_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9152_upack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9152_upack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack + set axi_ad9152_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9152_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9152_dma set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9152_dma @@ -26,10 +28,6 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9152_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9152_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9152_dma -set axi_ad9152_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9152_upack] -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9152_upack -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack - # adc peripherals set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr] @@ -37,14 +35,16 @@ set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr -set sys_ad9680_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_ad9680_rstgen] - -set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] - set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd +set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] + +set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack + set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma @@ -58,10 +58,6 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma -set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack] -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack - # shared transceiver core set util_daq3_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_daq3_xcvr] @@ -71,13 +67,25 @@ set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq3_xcvr ad_connect sys_cpu_resetn util_daq3_xcvr/up_rstn ad_connect sys_cpu_clk util_daq3_xcvr/up_clk +# reference clocks & resets + +create_bd_port -dir I tx_ref_clk_0 +create_bd_port -dir I rx_ref_clk_0 + +ad_xcvrpll tx_ref_clk_0 util_daq3_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_daq3_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9152_xcvr/up_pll_rst util_daq3_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq3_xcvr/up_cpll_rst_* + # connections (dac) ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd +ad_reconct util_daq3_xcvr/tx_0 axi_ad9152_jesd/gt0_tx +ad_reconct util_daq3_xcvr/tx_1 axi_ad9152_jesd/gt3_tx +ad_reconct util_daq3_xcvr/tx_2 axi_ad9152_jesd/gt1_tx +ad_reconct util_daq3_xcvr/tx_3 axi_ad9152_jesd/gt2_tx ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_core/tx_clk ad_connect axi_ad9152_jesd/tx_tdata axi_ad9152_core/tx_data -ad_connect util_daq3_xcvr/tx_out_clk_0 sys_ad9152_rstgen/slowest_sync_clk -ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/dac_clk ad_connect axi_ad9152_core/dac_enable_0 axi_ad9152_upack/dac_enable_0 ad_connect axi_ad9152_core/dac_ddata_0 axi_ad9152_upack/dac_data_0 @@ -85,6 +93,7 @@ ad_connect axi_ad9152_core/dac_valid_0 axi_ad9152_upack/dac_valid_0 ad_connect axi_ad9152_core/dac_enable_1 axi_ad9152_upack/dac_enable_1 ad_connect axi_ad9152_core/dac_ddata_1 axi_ad9152_upack/dac_data_1 ad_connect axi_ad9152_core/dac_valid_1 axi_ad9152_upack/dac_valid_1 +ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk ad_connect axi_ad9152_upack/dac_valid axi_ad9152_fifo/dac_valid ad_connect axi_ad9152_upack/dac_data axi_ad9152_fifo/dac_data ad_connect axi_ad9152_upack/dma_xfer_in axi_ad9152_fifo/dac_xfer_out @@ -104,17 +113,16 @@ ad_xcvrcon util_daq3_xcvr axi_ad9680_xcvr axi_ad9680_jesd ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof ad_connect axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data -ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk -ad_connect util_daq3_xcvr/tx_out_clk_0 sys_ad9680_rstgen/slowest_sync_clk -ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk -ad_connect sys_ad9680_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0 ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0 ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0 ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1 ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1 ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1 +ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk @@ -154,7 +162,5 @@ ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq -# unused - ad_connect axi_ad9152_fifo/dac_fifo_bypass GND diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl index 1c2f1794c..17d016d53 100644 --- a/projects/daq3/zc706/system_bd.tcl +++ b/projects/daq3/zc706/system_bd.tcl @@ -3,8 +3,8 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl -p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10 +p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 create_bd_port -dir I -type rst sys_rst create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 @@ -23,32 +23,3 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ source ../common/daq3_bd.tcl -# ila - -set mfifo_adc [create_bd_cell -type ip -vlnv analog.com:user:util_mfifo:1.0 mfifo_adc] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $mfifo_adc -set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc -set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc - -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc -set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc -set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_adc -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc - -ad_connect util_daq3_xcvr/up_tx_rst_done_0 mfifo_adc/din_rst -ad_connect util_daq3_xcvr/rx_out_clk_0 mfifo_adc/din_clk -ad_connect axi_ad9680_core/adc_valid_0 mfifo_adc/din_valid -ad_connect axi_ad9680_core/adc_data_0 mfifo_adc/din_data_0 -ad_connect axi_ad9680_core/adc_data_1 mfifo_adc/din_data_1 -ad_connect util_daq3_xcvr/up_tx_rst_done_0 mfifo_adc/dout_rst -ad_connect util_daq3_xcvr/rx_out_clk_0 mfifo_adc/dout_clk -ad_connect util_daq3_xcvr/rx_out_clk_0 ila_adc/clk -ad_connect mfifo_adc/dout_valid ila_adc/probe0 -ad_connect mfifo_adc/dout_data_0 ila_adc/probe1 -ad_connect mfifo_adc/dout_data_1 ila_adc/probe2 - - diff --git a/projects/daq3/zc706/system_top.v b/projects/daq3/zc706/system_top.v index 6273a25a0..217a9ce2c 100644 --- a/projects/daq3/zc706/system_top.v +++ b/projects/daq3/zc706/system_top.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps