diff --git a/projects/ad9671_fmc/a5gt/system_bd.qsys b/projects/ad9671_fmc/a5gt/system_bd.qsys
index ba4dd3291..378caad1c 100644
--- a/projects/ad9671_fmc/a5gt/system_bd.qsys
+++ b/projects/ad9671_fmc/a5gt/system_bd.qsys
@@ -78,14 +78,6 @@
          type = "String";
       }
    }
-   element sys_ethernet_dma_rx.csr
-   {
-      datum baseAddress
-      {
-         value = "86025280";
-         type = "String";
-      }
-   }
    element sys_ethernet_dma_tx.csr
    {
       datum baseAddress
@@ -94,6 +86,14 @@
          type = "String";
       }
    }
+   element sys_ethernet_dma_rx.csr
+   {
+      datum baseAddress
+      {
+         value = "86025280";
+         type = "String";
+      }
+   }
    element sys_jesd204b_s1.jesd204_rx_avs
    {
       datum baseAddress
@@ -144,11 +144,16 @@
          type = "String";
       }
    }
-   element sys_ethernet_desc_mem.s1
+   element sys_int_mem.s1
    {
-      datum baseAddress
+      datum _lockedAddress
       {
          value = "0";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "83886080";
          type = "String";
       }
    }
@@ -168,6 +173,14 @@
          type = "String";
       }
    }
+   element sys_ethernet_desc_mem.s1
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
    element sys_gpio.s1
    {
       datum baseAddress
@@ -176,16 +189,11 @@
          type = "String";
       }
    }
-   element sys_int_mem.s1
+   element sys_tcm_mem.s2
    {
-      datum _lockedAddress
-      {
-         value = "0";
-         type = "boolean";
-      }
       datum baseAddress
       {
-         value = "83886080";
+         value = "86016000";
          type = "String";
       }
    }
@@ -202,14 +210,6 @@
          type = "String";
       }
    }
-   element sys_tcm_mem.s2
-   {
-      datum baseAddress
-      {
-         value = "86016000";
-         type = "String";
-      }
-   }
    element axi_ad9671.s_axi
    {
       datum baseAddress
@@ -693,11 +693,7 @@
    internal="axi_ad9671.adc_dma_if"
    type="conduit"
    dir="end" />
- <interface
-   name="axi_ad9671_1_adc_mon_if"
-   internal="axi_ad9671.adc_mon_if"
-   type="conduit"
-   dir="end" />
+ <interface name="axi_ad9671_1_adc_mon_if" internal="axi_ad9671.adc_mon_if" />
  <module kind="clock_source" version="14.0" enabled="1" name="sys_clk">
   <parameter name="clockFrequency" value="50000000" />
   <parameter name="clockFrequencyKnown" value="true" />
@@ -1617,7 +1613,7 @@
   <parameter name="bitrev_en" value="false" />
   <parameter name="L" value="2" />
   <parameter name="M" value="8" />
-  <parameter name="N" value="16" />
+  <parameter name="N" value="14" />
   <parameter name="N_PRIME" value="16" />
   <parameter name="S" value="1" />
   <parameter name="K" value="4" />
diff --git a/projects/ad9671_fmc/a5gt/system_top.v b/projects/ad9671_fmc/a5gt/system_top.v
index 69b8020ca..f2f79d378 100644
--- a/projects/ad9671_fmc/a5gt/system_top.v
+++ b/projects/ad9671_fmc/a5gt/system_top.v
@@ -195,6 +195,7 @@ module system_top (
   reg               rx_sysref_m2 = 'd0;
   reg               rx_sysref_m3 = 'd0;
   reg               rx_sysref = 'd0;
+  reg               rx_sof_0 = 'd0;
 
   // internal clocks and resets
 
@@ -204,7 +205,6 @@ module system_top (
   wire              eth_tx_clk;
   wire              rx_clk;
   wire              adc_clk;
-  wire              adc1_clk;
 
   // internal registers
 
@@ -241,6 +241,7 @@ module system_top (
   wire    [  1:0]   rx_cal_busy_s;
   wire              rx_pll_locked_s;
   wire    [ 15:0]   rx_xcvr_status_s;
+  wire    [  1:0]   rx_data_sof;
 
   // ethernet transmit clock
 
@@ -295,7 +296,7 @@ module system_top (
     .sld_trigger_level_pipeline (1))
   i_signaltap (
     .acq_clk (rx_clk),
-    .acq_data_in ({rx_sysref, rx_sync, adc_data_s}),
+    .acq_data_in ({rx_sysref, rx_sync, rx_ip_data_s}),
     .acq_trigger_in ({rx_sysref, rx_sync}));
 
   genvar n;
@@ -305,10 +306,16 @@ module system_top (
     .rx_clk (rx_clk),
     .rx_sof (rx_ip_sof_s),
     .rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
+    .rx_data_sof(rx_data_sof[n]),
     .rx_data (rx_data_s[n*32+31:n*32]));
   end
   endgenerate
 
+  always @(rx_clk)
+  begin
+    rx_sof_0 <= |rx_data_sof ;
+  end
+
   assign rx_xcvr_status_s[15:11] = 5'd0;
   assign rx_xcvr_status_s[10:10] = rx_sync;
   assign rx_xcvr_status_s[ 9: 9] = rx_ready_s;
@@ -416,6 +423,7 @@ module system_top (
     .sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
     .axi_ad9671_1_xcvr_clk_clk (rx_clk),
     .axi_ad9671_1_xcvr_data_data (rx_data_s),
+    .axi_ad9671_1_xcvr_data_data_sof (rx_sof_0),
     .axi_ad9671_1_adc_clock_clk (adc_clk),
     .axi_ad9671_1_adc_dma_if_valid (adc_valid_s),
     .axi_ad9671_1_adc_dma_if_enable (adc_enable_s),