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ad_axis_inf_rx: Delete redundant local paramter 

All verilog file are using the Verilog-2001 standard to define
and/or declare ports. Definin a port width with a local parameter
is a bad practive, when this standard is used. Some simulators
will crash. Try to avoid it.
main
Istvan Csomortani 2017-07-06 09:37:54 +01:00
parent cfa22f36bc
commit 866d79dee2
1 changed files with 30 additions and 32 deletions
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24
library/common/ad_axis_inf_rx.v
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@ -45,43 +45,41 @@ module ad_axis_inf_rx #(
input rst, input rst,
input valid, input valid,
input last, input last,
input [DW:0] data, input [(DATA_WIDTH-1):0] data,
// xilinx interface // xilinx interface
output reg inf_valid, output reg inf_valid,
output reg inf_last, output reg inf_last,
output reg [DW:0] inf_data, output reg [(DATA_WIDTH-1):0] inf_data,
input inf_ready); input inf_ready);
localparam DW = DATA_WIDTH - 1;
// internal registers // internal registers
reg [ 2:0] wcnt = 'd0; reg [ 2:0] wcnt = 'd0;
reg wlast_0 = 'd0; reg wlast_0 = 'd0;
reg [DW:0] wdata_0 = 'd0; reg [(DATA_WIDTH-1):0] wdata_0 = 'd0;
reg wlast_1 = 'd0; reg wlast_1 = 'd0;
reg [DW:0] wdata_1 = 'd0; reg [(DATA_WIDTH-1):0] wdata_1 = 'd0;
reg wlast_2 = 'd0; reg wlast_2 = 'd0;
reg [DW:0] wdata_2 = 'd0; reg [(DATA_WIDTH-1):0] wdata_2 = 'd0;
reg wlast_3 = 'd0; reg wlast_3 = 'd0;
reg [DW:0] wdata_3 = 'd0; reg [(DATA_WIDTH-1):0] wdata_3 = 'd0;
reg wlast_4 = 'd0; reg wlast_4 = 'd0;
reg [DW:0] wdata_4 = 'd0; reg [(DATA_WIDTH-1):0] wdata_4 = 'd0;
reg wlast_5 = 'd0; reg wlast_5 = 'd0;
reg [DW:0] wdata_5 = 'd0; reg [(DATA_WIDTH-1):0] wdata_5 = 'd0;
reg wlast_6 = 'd0; reg wlast_6 = 'd0;
reg [DW:0] wdata_6 = 'd0; reg [(DATA_WIDTH-1):0] wdata_6 = 'd0;
reg wlast_7 = 'd0; reg wlast_7 = 'd0;
reg [DW:0] wdata_7 = 'd0; reg [(DATA_WIDTH-1):0] wdata_7 = 'd0;
reg [ 2:0] rcnt = 'd0; reg [ 2:0] rcnt = 'd0;
// internal signals // internal signals
wire inf_ready_s; wire inf_ready_s;
reg inf_last_s; reg inf_last_s;
reg [DW:0] inf_data_s; reg [(DATA_WIDTH-1):0] inf_data_s;
// write interface // write interface