library/common: Added DAC custom read/write interface in up_dac_common.

The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.

docs/regmap/adi_regmap_dac.txt

@@ -378,12 +378,51 @@ ENDFIELD
 ############################################################################################
 ############################################################################################
 
+REG
+0x0020
+REG_DAC_CUSTOM_RD
+DAC Read Configuration Data
+ENDREG
+
+FIELD
+[31:0] 0x00000000
+DAC_CUSTOM_RD[31:0]
+RO
+Custom Read of the available registers.
+ENDFIELD
+
+############################################################################################
+############################################################################################
+
+REG
+0x0021
+REG_DAC_CUSTOM_WR
+DAC Write Configuration Data
+ENDREG
+
+FIELD
+[31:0] 0x00000000
+DAC_CUSTOM_WR[31:0]
+RW
+Custom Write of the available registers.
+ENDFIELD
+
+############################################################################################
+############################################################################################
+
 REG
 0x0022
 REG_UI_STATUS
 User Interface Status
 ENDREG
 
+FIELD
+[4] 0x0
+IF_BUSY
+RO
+Interface busy. If set, indicates that the data interface is busy.
+ENDFIELD
+
 FIELD
 [1] 0x0
 UI_OVF
@@ -405,6 +444,22 @@ ENDFIELD
 ############################################################################################
 ############################################################################################
 
+REG
+0x0023
+REG_DAC_CUSTOM_CTRL
+DAC Control Configuration Data
+ENDREG
+
+FIELD
+[31:0] 0x00000000
+DAC_CUSTOM_CTRL[31:0]
+RW
+Custom Control of the available registers.
+ENDFIELD
+
+############################################################################################
+############################################################################################
+
 REG
 0x0028
 REG_USR_CNTRL_1

library/axi_ad5766/axi_ad5766.v

@@ -363,6 +363,10 @@ module axi_ad5766 #(
     .dac_sync (),
     .dac_frame (),
     .dac_clksel (),
+    .dac_custom_wr(),
+    .dac_custom_rd(32'b0),
+    .dac_custom_control(),
+    .dac_status_if_busy(1'b0),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (),

library/axi_ad9122/axi_ad9122_core.v

@@ -232,6 +232,10 @@ module axi_ad9122_core #(
     .dac_sync (dac_sync_out),
     .dac_frame (dac_frame_s),
     .dac_clksel (),
+    .dac_custom_wr(),
+    .dac_custom_rd(32'b0),
+    .dac_custom_control(),
+    .dac_status_if_busy(1'b0),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (),

library/axi_ad9361/axi_ad9361_tx.v

@@ -385,6 +385,10 @@ module axi_ad9361_tx #(
     .dac_sync (dac_sync),
     .dac_frame (),
     .dac_clksel (dac_clksel),
+    .dac_custom_wr(),
+    .dac_custom_rd(32'b0),
+    .dac_custom_control(),
+    .dac_status_if_busy(1'b0),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (dac_r1_mode),

library/axi_ad9739a/axi_ad9739a_core.v

@@ -179,6 +179,10 @@ module axi_ad9739a_core #(
     .dac_sync (dac_sync_s),
     .dac_frame (),
     .dac_clksel (),
+    .dac_custom_wr(),
+    .dac_custom_rd(32'b0),
+    .dac_custom_control(),
+    .dac_status_if_busy(1'b0),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (),

library/axi_ad9783/axi_ad9783_core.v

@@ -196,6 +196,10 @@ module axi_ad9783_core #(
     .dac_sync (dac_sync_s),
     .dac_frame (),
     .dac_clksel (),
+    .dac_custom_wr(),
+    .dac_custom_rd(32'b0),
+    .dac_custom_control(),
+    .dac_status_if_busy(1'b0),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (),

library/axi_ad9963/axi_ad9963_tx.v

@@ -216,6 +216,10 @@ module axi_ad9963_tx #(
     .dac_sync (dac_sync_out),
     .dac_frame (),
     .dac_clksel(),
+    .dac_custom_wr(),
+    .dac_custom_rd(32'b0),
+    .dac_custom_control(),
+    .dac_status_if_busy(1'b0),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (),

library/axi_adrv9001/axi_adrv9001_tx.v

@@ -384,6 +384,10 @@ module axi_adrv9001_tx #(
       .dac_ext_sync_arm (dac_ext_sync_arm),
       .dac_frame (),
       .dac_clksel (),
+      .dac_custom_wr(),
+      .dac_custom_rd(32'b0),
+      .dac_custom_control(),
+      .dac_status_if_busy(1'b0),
       .dac_par_type (),
       .dac_par_enb (),
       .dac_r1_mode (),

library/common/up_dac_common.v

@@ -95,6 +95,13 @@ module up_dac_common #(
   input               up_drp_ready,
   input               up_drp_locked,
 
+  // DAC custom read/write interface
+
+  output      [31:0]  dac_custom_wr,
+  output      [31:0]  dac_custom_control,
+  input       [31:0]  dac_custom_rd,
+  input               dac_status_if_busy,
+
   // user channel control
 
   output      [ 7:0]  up_usr_chanmax,
@@ -144,6 +151,8 @@ module up_dac_common #(
   reg     [15:0]  up_dac_datarate = 'd0;
   reg             up_dac_frame = 'd0;
   reg             up_dac_clksel = CLK_EDGE_SEL;
+  reg     [31:0]  up_dac_custom_wr = 'd0;
+  reg     [31:0]  up_dac_custom_control = 'd0;
   reg             up_status_unf = 'd0;
   reg     [ 7:0]  up_usr_chanmax_int = 'd0;
   reg     [31:0]  up_dac_gpio_out_int = 'd0;
@@ -164,6 +173,8 @@ module up_dac_common #(
   wire            up_rreq_s;
   wire            up_xfer_done_s;
   wire            up_status_s;
+  wire   [31:0]   up_dac_custom_rd;
+  wire            up_status_if_busy;
   wire            up_sync_in_status;
   wire            up_status_unf_s;
   wire            dac_sync_s;
@@ -212,6 +223,7 @@ module up_dac_common #(
       up_dac_datarate <= 'd0;
       up_dac_frame <= 'd0;
       up_dac_clksel <= CLK_EDGE_SEL;
+      up_dac_custom_control <= 'd0;
       up_pps_irq_mask <= 1'b1;
     end else begin
       up_dac_clk_enb_int <= ~up_dac_clk_enb;
@@ -280,6 +292,9 @@ module up_dac_common #(
       if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h18)) begin
         up_dac_clksel <= up_wdata[0];
       end
+      if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h23)) begin
+        up_dac_custom_control <= up_wdata;
+      end
     end
   end
 
@@ -350,6 +365,16 @@ module up_dac_common #(
   end
   endgenerate
 
+  always @(posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_dac_custom_wr <= 'd0;
+    end else begin
+      if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h21)) begin
+        up_dac_custom_wr <= up_wdata;
+      end
+    end
+  end
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
       up_status_unf <= 'd0;
@@ -439,11 +464,9 @@ module up_dac_common #(
                                   3'b0, up_dac_ext_sync_manual_req,
                                   4'b0,
                                   1'b0, up_dac_ext_sync_disarm, up_dac_ext_sync_arm, up_dac_sync};
-          7'h12: up_rdata_int <= {15'd0, up_dac_sdr_ddr_n,
+          7'h12: up_rdata_int <= {15'd0, up_dac_sdr_ddr_n, up_dac_symb_op, up_dac_symb_8_16b, 1'd0,
-                                  up_dac_symb_op, up_dac_symb_8_16b,
+                                  up_dac_num_lanes, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode,
-                                  1'd0, up_dac_num_lanes,
+                                  up_dac_datafmt, 4'd0};
-                                  up_dac_par_type, up_dac_par_enb, up_dac_r1_mode, up_dac_datafmt,
-                                  4'd0};
           7'h13: up_rdata_int <= {16'd0, up_dac_datarate};
           7'h14: up_rdata_int <= {31'd0, up_dac_frame};
           7'h15: up_rdata_int <= up_dac_clk_count_s;
@@ -455,12 +478,15 @@ module up_dac_common #(
           7'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status_s, 16'b0};
           7'h1e: up_rdata_int <= up_drp_wdata;
           7'h1f: up_rdata_int <= up_drp_rdata_hold_s;
-          7'h22: up_rdata_int <= {31'd0, up_status_unf};
+          7'h20: up_rdata_int <= up_dac_custom_rd;
+          7'h21: up_rdata_int <= up_dac_custom_wr;
+          7'h22: up_rdata_int <= {27'd0, up_status_if_busy, 3'd0, up_status_unf};
+          7'h23: up_rdata_int <= up_dac_custom_control;
           7'h28: up_rdata_int <= {24'd0, dac_usr_chanmax};
           7'h2e: up_rdata_int <= up_dac_gpio_in;
           7'h2f: up_rdata_int <= up_dac_gpio_out_int;
           7'h30: up_rdata_int <= up_pps_rcounter;
-          7'h31: up_rdata_int <= up_pps_status;
+          7'h31: up_rdata_int <= {31'd0,up_pps_status};
           7'h40: up_rdata_int <= up_timer;
           default: up_rdata_int <= 0;
         endcase
@@ -487,7 +513,7 @@ module up_dac_common #(
   // dac control & status
 
   up_xfer_cntrl #(
-    .DATA_WIDTH(35)
+    .DATA_WIDTH(99)
   ) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
@@ -500,6 +526,8 @@ module up_dac_common #(
                       up_dac_ext_sync_manual_req,
                       up_dac_sync,
                       up_dac_clksel,
+                      up_dac_custom_wr,
+                      up_dac_custom_control,
                       up_dac_frame,
                       up_dac_par_type,
                       up_dac_par_enb,
@@ -519,6 +547,8 @@ module up_dac_common #(
                       dac_ext_sync_manual_req,
                       dac_sync_s,
                       dac_clksel,
+                      dac_custom_wr,
+                      dac_custom_control,
                       dac_frame_s,
                       dac_par_type,
                       dac_par_enb,
@@ -533,18 +563,22 @@ module up_dac_common #(
   assign dac_rst = ~dac_rst_n;
 
   up_xfer_status #(
-    .DATA_WIDTH(3)
+    .DATA_WIDTH(36)
   ) i_xfer_status (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_status ({up_sync_in_status,
                       up_status_s,
-                      up_status_unf_s}),
+                      up_status_unf_s,
+                      up_status_if_busy,
+                      up_dac_custom_rd}),
     .d_rst (dac_rst_s),
     .d_clk (dac_clk),
     .d_data_status ({ dac_sync_in_status,
                       dac_status,
-                      dac_status_unf}));
+                      dac_status_unf,
+                      dac_status_if_busy,
+                      dac_custom_rd}));
 
   // generate frame and enable
 

library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v

@@ -232,6 +232,10 @@ module ad_ip_jesd204_tpl_dac_regmap #(
     .dac_sync_in_status (dac_sync_in_status),
     .dac_frame (),
     .dac_clksel (),
+    .dac_custom_wr(),
+    .dac_custom_rd(32'b0),
+    .dac_custom_control(),
+    .dac_status_if_busy(1'b0),
     .dac_par_type (),
     .dac_par_enb (),
     .dac_r1_mode (),