From 86cd484865ddf793e086121f61eb158ab03bcd8d Mon Sep 17 00:00:00 2001 From: PIoandan <128376819+PIoandan@users.noreply.github.com> Date: Wed, 7 Feb 2024 11:16:40 +0200 Subject: [PATCH] lib/axi_pwm_gen: Update pause_cnt logic (#1271) Signed-off-by: Ioan-daniel Pop --- library/axi_pwm_gen/axi_pwm_gen.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/library/axi_pwm_gen/axi_pwm_gen.sv b/library/axi_pwm_gen/axi_pwm_gen.sv index 929dfeb14..5202d9753 100644 --- a/library/axi_pwm_gen/axi_pwm_gen.sv +++ b/library/axi_pwm_gen/axi_pwm_gen.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -298,7 +298,8 @@ module axi_pwm_gen #( end end - assign pause_cnt = ((pwm_armed[1] | + assign pause_cnt = ((pwm_armed[0] | + pwm_armed[1] | pwm_armed[2] | pwm_armed[3] | pwm_armed[4] |