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lib/axi_pwm_gen: Update pause_cnt logic (#1271) 

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
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PIoandan 2024-02-07 11:16:40 +02:00 committed by GitHub
parent f01d7e5951
commit 86cd484865
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1 changed files with 3 additions and 2 deletions
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library/axi_pwm_gen/axi_pwm_gen.sv
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -298,7 +298,8 @@ module axi_pwm_gen #(
end
end
assign pause_cnt = ((pwm_armed[1] |
assign pause_cnt = ((pwm_armed[0] |
pwm_armed[1] |
pwm_armed[2] |
pwm_armed[3] |
pwm_armed[4] |