zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_logic_analyzer: Fix delayed trigger assertion condition

main
Adrian Costina 2017-06-19 10:58:22 +03:00
parent d840baee28
commit 871855c9ec
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
library/axi_logic_analyzer/axi_logic_analyzer.v
View File

@ -140,7 +140,7 @@ module axi_logic_analyzer (
assign up_rstn = s_axi_aresetn; assign up_rstn = s_axi_aresetn;
assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s : trigger_out_delayed; assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s : trigger_out_delayed;
assign trigger_out_delayed = trigger_delay == 32'h0 ? 1: 0; assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
generate generate
for (i = 0 ; i < 16; i = i + 1) begin for (i = 0 ; i < 16; i = i + 1) begin