jesd204_rx: Interrupt for unexpected lane status error

library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v

@@ -99,6 +99,7 @@ module axi_jesd204_rx #(
   input core_event_sysref_alignment_error,
   input core_event_sysref_edge,
   input core_event_frame_alignment_error,
+  input core_event_unexpected_lane_state_error,
 
   output [6:0] core_ctrl_err_statistics_mask,
   output core_ctrl_err_statistics_reset,
@@ -145,15 +146,22 @@ wire [7:0] up_cfg_frame_align_err_threshold;
 wire up_reset;
 wire up_reset_synchronizer;
 wire up_event_frame_alignment_error;
+wire up_event_unexpected_lane_state_error;
 
-sync_event i_sync_frame_align_err (
+sync_event #(
+  .NUM_OF_EVENTS (2)
+) i_sync_frame_align_err (
   .in_clk(core_clk),
-  .in_event(core_event_frame_alignment_error),
+  .in_event({core_event_unexpected_lane_state_error,
+             core_event_frame_alignment_error}),
   .out_clk(s_axi_aclk),
-  .out_event(up_event_frame_alignment_error)
+  .out_event({up_event_unexpected_lane_state_error,
+              up_event_frame_alignment_error})
 );
 
-assign up_irq_trigger = {4'b0,up_event_frame_alignment_error};
+assign up_irq_trigger = {3'b0,
+                         up_event_unexpected_lane_state_error,
+                         up_event_frame_alignment_error};
 
 up_axi #(
   .AXI_ADDRESS_WIDTH (14)

library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl

@@ -107,6 +107,7 @@ adi_add_bus "rx_event" "slave" \
     { "core_event_sysref_alignment_error" "sysref_alignment_error" } \
     { "core_event_sysref_edge" "sysref_edge" } \
     { "core_event_frame_alignment_error" "frame_alignment_error" } \
+    { "core_event_unexpected_lane_state_error" "unexpected_lane_state_error" } \
   }
 
 adi_add_bus "rx_status" "slave" \

library/jesd204/interfaces/interfaces_ip.tcl

@@ -111,3 +111,4 @@ adi_if_define "jesd204_rx_event"
 adi_if_ports output 1 sysref_alignment_error
 adi_if_ports output 1 sysref_edge
 adi_if_ports output 1 frame_alignment_error
+adi_if_ports output 1 unexpected_lane_state_error

library/jesd204/jesd204_rx/jesd204_rx.v

@@ -71,6 +71,7 @@ module jesd204_rx #(
   output event_sysref_alignment_error,
   output event_sysref_edge,
   output event_frame_alignment_error,
+  output event_unexpected_lane_state_error,
 
   output [NUM_LINKS-1:0] sync,
 
@@ -282,6 +283,9 @@ genvar i;
 
 if (LINK_MODE[0] == 1) begin : mode_8b10b
 
+wire unexpected_lane_state_error;
+reg unexpected_lane_state_error_d = 1'b0;
+
 jesd204_rx_ctrl #(
   .NUM_LANES(NUM_LANES),
   .NUM_LINKS(NUM_LINKS)
@@ -400,6 +404,15 @@ end
 
 assign event_frame_alignment_error = |event_frame_alignment_error_per_lane;
 
+/* If one of the enabled lanes falls out of DATA phase while the link is in DATA phase
+ * report an error event */
+assign unexpected_lane_state_error = |(~(cgs_ready|cfg_lanes_disable)) & &status_ctrl_state;
+always @(posedge clk) begin
+  unexpected_lane_state_error_d <= unexpected_lane_state_error;
+end
+assign event_unexpected_lane_state_error = unexpected_lane_state_error & ~unexpected_lane_state_error_d;
+
+
 /* Delay matching based on the number of pipeline stages */
 reg [NUM_LANES-1:0] ifs_ready_d1 = 1'b0;
 reg [NUM_LANES-1:0] ifs_ready_d2 = 1'b0;
@@ -454,7 +467,8 @@ jesd204_rx_ctrl_64b  #(
   .all_emb_lock(all_emb_lock),
   .buffer_release_n(buffer_release_n),
 
-  .status_state(status_ctrl_state)
+  .status_state(status_ctrl_state),
+  .event_unexpected_lane_state_error(event_unexpected_lane_state_error)
 );
 
 for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane

library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v

@@ -59,7 +59,8 @@ module jesd204_rx_ctrl_64b #(
   output all_emb_lock,
   input buffer_release_n,
 
-  output [1:0] status_state
+  output [1:0] status_state,
+  output reg event_unexpected_lane_state_error
 );
 
 
@@ -86,6 +87,7 @@ assign all_emb_lock = &emb_lock_masked;
 always @(*) begin
   next_state = state;
   rst_good_cnt = 1'b1;
+  event_unexpected_lane_state_error = 1'b0;
   case (state)
     STATE_RESET:
       next_state = STATE_WAIT_BS;
@@ -108,8 +110,10 @@ always @(*) begin
     STATE_DATA:
       if (~all_block_sync) begin
         next_state = STATE_WAIT_BS;
+        event_unexpected_lane_state_error = 1'b1;
       end else if (~all_emb_lock | buffer_release_n) begin
         next_state = STATE_BLOCK_SYNC;
+        event_unexpected_lane_state_error = 1'b1;
       end
   endcase
 end

library/jesd204/jesd204_rx/jesd204_rx_ip.tcl

@@ -144,6 +144,7 @@ adi_add_bus "rx_event" "master" \
     { "event_sysref_alignment_error" "sysref_alignment_error" } \
     { "event_sysref_edge" "sysref_edge" } \
     { "event_frame_alignment_error" "frame_alignment_error" } \
+    { "event_unexpected_lane_state_error" "unexpected_lane_state_error" } \
   }
 
 adi_add_bus_clock "clk" "rx_cfg:rx_ilas_config:rx_event:rx_status:rx_data" "reset"