From 87bec07a22582e4f2d4fd8c76ef394ac09510b08 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Jun 2014 09:42:45 -0400 Subject: [PATCH] ad9625: added multi-sync support --- library/axi_ad9625/axi_ad9625.v | 30 +++++------ library/axi_ad9625/axi_ad9625_if.v | 81 +++++++++++++++++++++++++++- library/axi_ad9625/axi_ad9625_ip.tcl | 1 + 3 files changed, 92 insertions(+), 20 deletions(-) diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v index 9d5bdf0a5..d071cb389 100755 --- a/library/axi_ad9625/axi_ad9625.v +++ b/library/axi_ad9625/axi_ad9625.v @@ -56,6 +56,9 @@ module axi_ad9625 ( adc_dovf, adc_dunf, adc_enable, + adc_sref, + adc_raddr_in, + adc_raddr_out, // axi interface @@ -77,12 +80,7 @@ module axi_ad9625 ( s_axi_rvalid, s_axi_rresp, s_axi_rdata, - s_axi_rready, - - // debug signals - - adc_mon_valid, - adc_mon_data); + s_axi_rready); parameter PCORE_ID = 0; parameter PCORE_DEVICE_TYPE = 0; @@ -106,6 +104,9 @@ module axi_ad9625 ( input adc_dovf; input adc_dunf; output adc_enable; + output [ 15:0] adc_sref; + input [ 3:0] adc_raddr_in; + output [ 3:0] adc_raddr_out; // axi interface @@ -129,11 +130,6 @@ module axi_ad9625 ( output [ 31:0] s_axi_rdata; input s_axi_rready; - // debug signals - - output adc_mon_valid; - output [191:0] adc_mon_data; - // internal registers reg adc_dsync = 'd0; @@ -171,11 +167,6 @@ module axi_ad9625 ( assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; - // monitor signals - - assign adc_mon_valid = 1'b1; - assign adc_mon_data = adc_data_s; - // adc channels - dma interface always @(posedge adc_clk) begin @@ -198,14 +189,17 @@ module axi_ad9625 ( // main (device interface) - axi_ad9625_if i_if ( + axi_ad9625_if #(.PCORE_ID(PCORE_ID)) i_if ( .rx_clk (rx_clk), .rx_data (rx_data), .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_s), .adc_or (adc_or_s), - .adc_status (adc_status_s)); + .adc_status (adc_status_s), + .adc_sref (adc_sref), + .adc_raddr_in (adc_raddr_in), + .adc_raddr_out (adc_raddr_out)); // channel diff --git a/library/axi_ad9625/axi_ad9625_if.v b/library/axi_ad9625/axi_ad9625_if.v index 3e5c82183..c3fa60af9 100755 --- a/library/axi_ad9625/axi_ad9625_if.v +++ b/library/axi_ad9625/axi_ad9625_if.v @@ -54,7 +54,12 @@ module axi_ad9625_if ( adc_rst, adc_data, adc_or, - adc_status); + adc_status, + adc_sref, + adc_raddr_in, + adc_raddr_out); + + parameter PCORE_ID = 0; // jesd interface // rx_clk is ref_clk/4 @@ -69,13 +74,27 @@ module axi_ad9625_if ( output [191:0] adc_data; output adc_or; output adc_status; + output [ 15:0] adc_sref; + input [ 3:0] adc_raddr_in; + output [ 3:0] adc_raddr_out; // internal registers + reg [191:0] adc_data = 'd0; + reg [ 15:0] adc_sref = 'd0; + reg [191:0] adc_data_cur = 'd0; + reg [191:0] adc_data_prv = 'd0; + reg [ 3:0] adc_waddr = 'd0; + reg [ 3:0] adc_raddr_out = 'd0; + reg [191:0] adc_wdata = 'd0; reg adc_status = 'd0; // internal signals + wire [191:0] adc_rdata_s; + wire [ 3:0] adc_raddr_s; + wire [ 15:0] adc_sref_s; + wire [191:0] adc_data_s; wire [ 15:0] adc_data_s15_s; wire [ 15:0] adc_data_s14_s; wire [ 15:0] adc_data_s13_s; @@ -101,12 +120,59 @@ module axi_ad9625_if ( wire [ 31:0] rx_data6_s; wire [ 31:0] rx_data7_s; + // nothing much to do on clock & over-range + assign adc_clk = rx_clk; assign adc_or = 1'b0; + // synchronization mode, multiple instances + + assign adc_raddr_s = (PCORE_ID == 0) ? adc_raddr_out : adc_raddr_in; + + always @(posedge rx_clk) begin + adc_data <= adc_rdata_s; + if (adc_sref_s != 16'd0) begin + adc_sref <= adc_sref_s; + end + adc_data_cur <= adc_data_s; + adc_data_prv <= adc_data_cur; + if (adc_sref_s == 16'd0) begin + adc_waddr <= adc_waddr + 1'b1; + adc_raddr_out <= adc_raddr_out + 1'b1; + end else begin + adc_waddr <= 4'h0; + adc_raddr_out <= 4'h8; + end + case (adc_sref) + 16'h8000: adc_wdata <= {adc_data_cur[179:0], adc_data_prv[191:180]}; + 16'h4000: adc_wdata <= {adc_data_cur[167:0], adc_data_prv[191:168]}; + 16'h2000: adc_wdata <= {adc_data_cur[155:0], adc_data_prv[191:156]}; + 16'h1000: adc_wdata <= {adc_data_cur[143:0], adc_data_prv[191:144]}; + 16'h0800: adc_wdata <= {adc_data_cur[131:0], adc_data_prv[191:132]}; + 16'h0400: adc_wdata <= {adc_data_cur[119:0], adc_data_prv[191:120]}; + 16'h0200: adc_wdata <= {adc_data_cur[107:0], adc_data_prv[191:108]}; + 16'h0100: adc_wdata <= {adc_data_cur[ 95:0], adc_data_prv[191: 96]}; + 16'h0080: adc_wdata <= {adc_data_cur[ 83:0], adc_data_prv[191: 84]}; + 16'h0040: adc_wdata <= {adc_data_cur[ 71:0], adc_data_prv[191: 72]}; + 16'h0020: adc_wdata <= {adc_data_cur[ 59:0], adc_data_prv[191: 60]}; + 16'h0010: adc_wdata <= {adc_data_cur[ 47:0], adc_data_prv[191: 48]}; + 16'h0008: adc_wdata <= {adc_data_cur[ 35:0], adc_data_prv[191: 36]}; + 16'h0004: adc_wdata <= {adc_data_cur[ 23:0], adc_data_prv[191: 24]}; + 16'h0002: adc_wdata <= {adc_data_cur[ 11:0], adc_data_prv[191: 12]}; + default: adc_wdata <= adc_data_prv; + endcase + end + // samples only - assign adc_data = {adc_data_s15_s[11:0], adc_data_s14_s[11:0], + assign adc_sref_s = {adc_data_s15_s[14], adc_data_s14_s[14], + adc_data_s13_s[14], adc_data_s12_s[14], adc_data_s11_s[14], + adc_data_s10_s[14], adc_data_s09_s[14], adc_data_s08_s[14], + adc_data_s07_s[14], adc_data_s06_s[14], adc_data_s05_s[14], + adc_data_s04_s[14], adc_data_s03_s[14], adc_data_s02_s[14], + adc_data_s01_s[14], adc_data_s00_s[14]}; + + assign adc_data_s = {adc_data_s15_s[11:0], adc_data_s14_s[11:0], adc_data_s13_s[11:0], adc_data_s12_s[11:0], adc_data_s11_s[11:0], adc_data_s10_s[11:0], adc_data_s09_s[11:0], adc_data_s08_s[11:0], adc_data_s07_s[11:0], adc_data_s06_s[11:0], adc_data_s05_s[11:0], @@ -151,6 +217,17 @@ module axi_ad9625_if ( end end + // alignment fifo + + ad_mem #(.ADDR_WIDTH(4), .DATA_WIDTH(192)) i_mem ( + .clka (rx_clk), + .wea (1'b1), + .addra (adc_waddr), + .dina (adc_wdata), + .clkb (rx_clk), + .addrb (adc_raddr_s), + .doutb (adc_rdata_s)); + endmodule // *************************************************************************** diff --git a/library/axi_ad9625/axi_ad9625_ip.tcl b/library/axi_ad9625/axi_ad9625_ip.tcl index 56c226f2c..185038ee6 100755 --- a/library/axi_ad9625/axi_ad9625_ip.tcl +++ b/library/axi_ad9625/axi_ad9625_ip.tcl @@ -6,6 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9625 adi_ip_files axi_ad9625 [list \ "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_mem.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \