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util_dacfifo: Cosmetic changes

main
Istvan Csomortani 2015-09-24 11:22:22 +03:00
parent 7853843036
commit 884973fdbb
1 changed files with 20 additions and 22 deletions
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42
library/util_dacfifo/util_dacfifo.v
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@ -62,41 +62,39 @@ module util_dacfifo (
parameter ADDRESS_WIDTH = 6;
parameter DATA_WIDTH = 128;
// local parameters
// port definitions
// DMA interface
input dma_clk;
input dma_rst;
input dma_valid;
input [(DATA_WIDTH-1):0] dma_data;
output dma_ready;
input dma_xfer_req;
input dma_xfer_last;
input dma_clk;
input dma_rst;
input dma_valid;
input [(DATA_WIDTH-1):0] dma_data;
output dma_ready;
input dma_xfer_req;
input dma_xfer_last;
// DAC interface
input dac_clk;
input dac_valid;
output [(DATA_WIDTH-1):0] dac_data;
input dac_clk;
input dac_valid;
output [(DATA_WIDTH-1):0] dac_data;
// internal registers
reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_d = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_2d = 'b0;
reg dma_xfer_req_ff = 1'b0;
reg dma_ready = 1'b0;
reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_d = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_2d = 'b0;
reg dma_xfer_req_ff = 1'b0;
reg dma_ready = 1'b0;
reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0;
reg [(DATA_WIDTH-1):0] dac_data = 'b0;
reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0;
reg [(DATA_WIDTH-1):0] dac_data = 'b0;
// internal wires
wire dma_wren;
wire [(DATA_WIDTH-1):0] dac_data_s;
wire dma_wren;
wire [(DATA_WIDTH-1):0] dac_data_s;
// write interface
always @(posedge dma_clk) begin