From 884973fdbb4ffeb290ba61fe8b5f3412fa5e8f4a Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 24 Sep 2015 11:22:22 +0300 Subject: [PATCH] util_dacfifo: Cosmetic changes --- library/util_dacfifo/util_dacfifo.v | 42 ++++++++++++++--------------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v index f15c93043..bc01dcd7f 100644 --- a/library/util_dacfifo/util_dacfifo.v +++ b/library/util_dacfifo/util_dacfifo.v @@ -62,41 +62,39 @@ module util_dacfifo ( parameter ADDRESS_WIDTH = 6; parameter DATA_WIDTH = 128; - // local parameters - // port definitions // DMA interface - input dma_clk; - input dma_rst; - input dma_valid; - input [(DATA_WIDTH-1):0] dma_data; - output dma_ready; - input dma_xfer_req; - input dma_xfer_last; + input dma_clk; + input dma_rst; + input dma_valid; + input [(DATA_WIDTH-1):0] dma_data; + output dma_ready; + input dma_xfer_req; + input dma_xfer_last; // DAC interface - input dac_clk; - input dac_valid; - output [(DATA_WIDTH-1):0] dac_data; + input dac_clk; + input dac_valid; + output [(DATA_WIDTH-1):0] dac_data; // internal registers - reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0; - reg [(ADDRESS_WIDTH-1):0] dma_lastaddr = 'b0; - reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_d = 'b0; - reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_2d = 'b0; - reg dma_xfer_req_ff = 1'b0; - reg dma_ready = 1'b0; + reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0; + reg [(ADDRESS_WIDTH-1):0] dma_lastaddr = 'b0; + reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_d = 'b0; + reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_2d = 'b0; + reg dma_xfer_req_ff = 1'b0; + reg dma_ready = 1'b0; - reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0; - reg [(DATA_WIDTH-1):0] dac_data = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0; + reg [(DATA_WIDTH-1):0] dac_data = 'b0; // internal wires - wire dma_wren; - wire [(DATA_WIDTH-1):0] dac_data_s; + wire dma_wren; + wire [(DATA_WIDTH-1):0] dac_data_s; // write interface always @(posedge dma_clk) begin