util_gtlb: updates for latest axi_jesd_gt
parent
92b7570864
commit
88568c21e1
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@ -47,7 +47,6 @@ module util_gtlb (
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output qpll0_rst,
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output qpll0_ref_clk_in,
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input pll_rst_0,
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output cpll_rst_m_0,
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output cpll_ref_clk_in_0,
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@ -66,6 +65,7 @@ module util_gtlb (
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output rx_0_n,
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input rx_rst_0,
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output rx_rst_m_0,
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input rx_pll_rst_0,
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input rx_gt_rst_0,
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output rx_gt_rst_m_0,
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input rx_pll_locked_0,
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@ -99,6 +99,7 @@ module util_gtlb (
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input tx_0_n,
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input tx_rst_0,
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output tx_rst_m_0,
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input tx_pll_rst_0,
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input tx_gt_rst_0,
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output tx_gt_rst_m_0,
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input tx_pll_locked_0,
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@ -201,9 +202,9 @@ module util_gtlb (
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// defaults
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assign qpll0_rst = pll_rst_0;
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assign qpll0_rst = tx_pll_rst_0 | rx_pll_rst_0;
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assign qpll0_ref_clk_in = qpll_ref_clk;
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assign cpll_rst_m_0 = pll_rst_0;
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assign cpll_rst_m_0 = tx_pll_rst_0 | rx_pll_rst_0;
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assign cpll_ref_clk_in_0 = cpll_ref_clk;
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assign rx_0_p = rx_p;
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@ -22,7 +22,6 @@ adi_if_infer_bus ADI:user:if_gt_qpll master gt_qpll_0 [list \
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for {set n 0} {$n < 1} {incr n} {
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adi_if_infer_bus ADI:user:if_gt_pll master gt_pll_${n} [list \
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"pll_rst pll_rst_${n} "\
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"cpll_rst_m cpll_rst_m_${n} "\
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"cpll_ref_clk_in cpll_ref_clk_in_${n} "]
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@ -37,6 +36,7 @@ for {set n 0} {$n < 1} {incr n} {
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"rx_n rx_${n}_n "\
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"rx_rst rx_rst_${n} "\
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"rx_rst_m rx_rst_m_${n} "\
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"rx_pll_rst rx_pll_rst_${n} "\
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"rx_gt_rst rx_gt_rst_${n} "\
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"rx_gt_rst_m rx_gt_rst_m_${n} "\
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"rx_pll_locked rx_pll_locked_${n} "\
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@ -67,6 +67,7 @@ for {set n 0} {$n < 1} {incr n} {
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"tx_n tx_${n}_n "\
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"tx_rst tx_rst_${n} "\
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"tx_rst_m tx_rst_m_${n} "\
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"tx_pll_rst tx_pll_rst_${n} "\
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"tx_gt_rst tx_gt_rst_${n} "\
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"tx_gt_rst_m tx_gt_rst_m_${n} "\
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"tx_pll_locked tx_pll_locked_${n} "\
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