diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index c57b87ccb..eaf06382e 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -65,6 +65,7 @@ module axi_ad9361 #(
   parameter   DAC_USERPORTS_DISABLE = 0,
   parameter   DAC_IQCORRECTION_DISABLE = 0,
   parameter   IO_DELAY_GROUP = "dev_if_delay_group",
+  parameter   IODELAY_CTRL = 1,
   parameter   MIMO_ENABLE = 0,
   parameter   USE_SSI_CLK = 1,
   parameter   DELAY_REFCLK_FREQUENCY = 200,
@@ -335,6 +336,7 @@ module axi_ad9361 #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IO_DELAY_GROUP (IO_DELAY_GROUP),
+    .IODELAY_CTRL (IODELAY_CTRL),
     .CLK_DESKEW (MIMO_ENABLE),
     .USE_SSI_CLK (USE_SSI_CLK),
     .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
@@ -399,6 +401,7 @@ module axi_ad9361 #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
     .IO_DELAY_GROUP (IO_DELAY_GROUP),
+    .IODELAY_CTRL (IODELAY_CTRL),
     .CLK_DESKEW (MIMO_ENABLE),
     .USE_SSI_CLK (USE_SSI_CLK),
     .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
diff --git a/library/axi_ad9361/intel/axi_ad9361_cmos_if.v b/library/axi_ad9361/intel/axi_ad9361_cmos_if.v
index 0f9b54fde..b95e6e9f9 100644
--- a/library/axi_ad9361/intel/axi_ad9361_cmos_if.v
+++ b/library/axi_ad9361/intel/axi_ad9361_cmos_if.v
@@ -44,6 +44,7 @@ module axi_ad9361_cmos_if #(
 
   // Dummy parameters, required keep the code consistency(used on Xilinx)
   parameter   IO_DELAY_GROUP = "dev_if_delay_group",
+  parameter   IODELAY_CTRL = 1,
   parameter   DELAY_REFCLK_FREQUENCY = 0) (
 
   // physical interface (receive)
diff --git a/library/axi_ad9361/intel/axi_ad9361_lvds_if.v b/library/axi_ad9361/intel/axi_ad9361_lvds_if.v
index 08bca96bb..573fc915e 100644
--- a/library/axi_ad9361/intel/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/intel/axi_ad9361_lvds_if.v
@@ -44,6 +44,7 @@ module axi_ad9361_lvds_if #(
   // Dummy parameters, required keep the code consistency(used on Xilinx)
   parameter   USE_SSI_CLK = 1,
   parameter   IO_DELAY_GROUP = "dev_if_delay_group",
+  parameter   IODELAY_CTRL = 1,
   parameter   DELAY_REFCLK_FREQUENCY = 0,
   parameter   RX_NODPA = 0) (
 
diff --git a/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
index 62337daed..2d912e92b 100644
--- a/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
+++ b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
@@ -40,6 +40,7 @@ module axi_ad9361_cmos_if #(
   parameter   FPGA_TECHNOLOGY = 0,
   parameter   DAC_IODELAY_ENABLE = 0,
   parameter   IO_DELAY_GROUP = "dev_if_delay_group",
+  parameter   IODELAY_CTRL = 1,
   parameter   CLK_DESKEW = 0,
   parameter   USE_SSI_CLK = 1,
   parameter   DELAY_REFCLK_FREQUENCY = 200) (
@@ -460,7 +461,7 @@ module axi_ad9361_cmos_if #(
   ad_data_in #(
     .SINGLE_ENDED (1),
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
-    .IODELAY_CTRL (1),
+    .IODELAY_CTRL (IODELAY_CTRL),
     .IODELAY_GROUP (IO_DELAY_GROUP),
     .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
   i_rx_frame (
diff --git a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
index 71b0d863a..7ab781910 100644
--- a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
@@ -40,6 +40,7 @@ module axi_ad9361_lvds_if #(
   parameter   FPGA_TECHNOLOGY = 0,
   parameter   DAC_IODELAY_ENABLE = 0,
   parameter   IO_DELAY_GROUP = "dev_if_delay_group",
+  parameter   IODELAY_CTRL = 1,
   parameter   CLK_DESKEW = 0,
   parameter   USE_SSI_CLK = 1,
   parameter   DELAY_REFCLK_FREQUENCY = 200,
@@ -474,7 +475,7 @@ module axi_ad9361_lvds_if #(
 
   ad_data_in #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
-    .IODELAY_CTRL (1),
+    .IODELAY_CTRL (IODELAY_CTRL),
     .IODELAY_GROUP (IO_DELAY_GROUP),
     .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
   i_rx_frame (