library: remove all constraints for now
parent
27153fff41
commit
88a3b7f8fd
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@ -1,9 +1,4 @@
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create_clock -period [expr 1000/250] -name tx_clk [get_ports tx_clk]
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create_clock -period [expr 1000/100] -name s_axi_aclk [get_ports s_axi_aclk]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports tx_clk]]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
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@ -20,7 +20,8 @@ adi_ip_files axi_ad9144 [list \
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"axi_ad9144_channel.v" \
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"axi_ad9144_core.v" \
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"axi_ad9144_if.v" \
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"axi_ad9144.v" ]
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"axi_ad9144.v" \
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"axi_ad9144_constr.xdc" ]
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adi_ip_properties axi_ad9144
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adi_ip_constraints axi_ad9144 [list \
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@ -1,9 +1,4 @@
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create_clock -period [expr 1000/250] -name rx_clk [get_ports rx_clk]
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create_clock -period [expr 1000/100] -name s_axi_aclk [get_ports s_axi_aclk]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports rx_clk]]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
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@ -19,7 +19,8 @@ adi_ip_files axi_ad9234 [list \
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"axi_ad9234_pnmon.v" \
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"axi_ad9234_channel.v" \
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"axi_ad9234_if.v" \
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"axi_ad9234.v" ]
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"axi_ad9234.v" \
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"axi_ad9234_constr.xdc" ]
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adi_ip_properties axi_ad9234
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adi_ip_constraints axi_ad9234 [list \
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@ -1,9 +1,4 @@
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create_clock -period [expr 1000/250] -name rx_clk [get_ports rx_clk]
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create_clock -period [expr 1000/100] -name s_axi_aclk [get_ports s_axi_aclk]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports rx_clk]]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
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@ -19,7 +19,8 @@ adi_ip_files axi_ad9680 [list \
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"axi_ad9680_pnmon.v" \
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"axi_ad9680_channel.v" \
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"axi_ad9680_if.v" \
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"axi_ad9680.v" ]
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"axi_ad9680.v" \
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"axi_ad9680_constr.xdc" ]
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adi_ip_properties axi_ad9680
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adi_ip_constraints axi_ad9680 [list \
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@ -1,15 +1,4 @@
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create_clock -period [expr 1000/100] -name s_axi_aclk [get_ports s_axi_aclk]
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create_clock -period [expr 1000/200] -name fifo_wr_clk [get_ports fifo_wr_clk]
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create_clock -period [expr 1000/200] -name fifo_rd_clk [get_ports fifo_rd_clk]
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create_clock -period [expr 1000/200] -name m_src_axi_aclk [get_ports m_src_axi_aclk]
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create_clock -period [expr 1000/200] -name m_dest_axi_aclk [get_ports m_dest_axi_aclk]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports fifo_wr_clk]]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports fifo_rd_clk]]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_src_axi_aclk]]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_dest_axi_aclk]]
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@ -28,7 +28,8 @@ adi_ip_files axi_dmac [list \
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"splitter.v" \
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"response_generator.v" \
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"axi_dmac.v" \
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"axi_repack.v" ]
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"axi_repack.v" \
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"axi_dmac_constr.xdc" ]
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adi_ip_properties axi_dmac
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adi_ip_constraints axi_dmac [list \
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@ -1,10 +1,3 @@
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create_clock -period [expr 1000/150] -name hdmi_clk [get_ports hdmi_clk]
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create_clock -period [expr 1000/100] -name s_axi_aclk [get_ports s_axi_aclk]
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create_clock -period [expr 1000/200] -name m_axis_mm2s_clk [get_ports m_axis_mm2s_clk]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports hdmi_clk]]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_axis_mm2s_clk]]
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@ -1,25 +1,2 @@
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create_clock -period [expr 1000/250] -name rx_clk [get_ports rx_clk]
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create_clock -period [expr 1000/250] -name tx_clk [get_ports tx_clk]
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create_clock -period [expr 1000/100] -name drp_clk [get_ports drp_clk]
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create_clock -period [expr 1000/500] -name ref_clk_c [get_ports ref_clk_c]
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create_clock -period [expr 1000/500] -name ref_clk_q [get_ports ref_clk_q]
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create_clock -period [expr 1000/100] -name s_axi_aclk [get_ports s_axi_aclk]
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create_clock -period [expr 1000/100] -name m_axi_aclk [get_ports m_axi_aclk]
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set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports rx_clk]]
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set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports tx_clk]]
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set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports drp_clk]]
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set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports ref_clk_c]]
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set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports ref_clk_q]]
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set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
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set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports m_axi_aclk]]
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set_false_path -through [get_nets rx_rst]
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set_false_path -through [get_nets tx_rst]
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set_false_path -through [get_nets */drp_rst]
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set_false_path -through [get_nets */gt_rx_rst]
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set_false_path -through [get_nets */gt_tx_rst]
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set_false_path -through [get_nets */gt_pll_rst]
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@ -15,7 +15,8 @@ adi_ip_files axi_jesd_gt [list \
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"$ad_hdl_dir/library/common/up_xfer_status.v" \
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"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
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"$ad_hdl_dir/library/common/up_gt.v" \
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"axi_jesd_gt.v" ]
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"axi_jesd_gt.v" \
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"axi_jesd_gt_constr.xdc" ]
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adi_ip_properties axi_jesd_gt
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adi_ip_constraints axi_jesd_gt [list \
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@ -1,8 +1,4 @@
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports spdif_data_clk]]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports S_AXIS_ACLK]]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports DMA_REQ_ACLK]]
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set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports S_AXI_ACLK]]
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@ -11,7 +11,8 @@ adi_ip_files axi_spdif_tx [list \
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"$ad_hdl_dir/library/common/dma_fifo.vhd" \
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"tx_package.vhd" \
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"tx_encoder.vhd" \
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"axi_spdif_tx.vhd" ]
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"axi_spdif_tx.vhd" \
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"axi_spdif_tx_constr.xdc" ]
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adi_ip_properties_lite axi_spdif_tx
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Loading…
Reference in New Issue