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util_dac_unpack: Delete unused IP core

main
Istvan Csomortani 2016-07-20 13:24:36 +03:00
parent 634924246a
commit 8902a31ca6
4 changed files with 0 additions and 409 deletions
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46
library/util_dac_unpack/Makefile
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := util_dac_unpack_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += util_dac_unpack.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all clean clean-all
all: util_dac_unpack.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
util_dac_unpack.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) util_dac_unpack_ip.tcl >> util_dac_unpack_ip.log 2>&1
####################################################################################
####################################################################################

236
library/util_dac_unpack/util_dac_unpack.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_dac_unpack (
clk,
dac_enable_00,
dac_valid_00,
dac_data_00,
dac_enable_01,
dac_valid_01,
dac_data_01,
dac_enable_02,
dac_valid_02,
dac_data_02,
dac_enable_03,
dac_valid_03,
dac_data_03,
dac_enable_04,
dac_valid_04,
dac_data_04,
dac_enable_05,
dac_valid_05,
dac_data_05,
dac_enable_06,
dac_valid_06,
dac_data_06,
dac_enable_07,
dac_valid_07,
dac_data_07,
fifo_valid,
dma_rd,
dma_data);
parameter NUM_OF_CHANNELS = 8; // valid values are 4 and 8
parameter DATA_WIDTH = 16;
input clk;
input dac_enable_00;
input dac_valid_00;
output [DATA_WIDTH-1:0] dac_data_00;
input dac_enable_01;
input dac_valid_01;
output [DATA_WIDTH-1:0] dac_data_01;
input dac_enable_02;
input dac_valid_02;
output [DATA_WIDTH-1:0] dac_data_02;
input dac_enable_03;
input dac_valid_03;
output [DATA_WIDTH-1:0] dac_data_03;
input dac_enable_04;
input dac_valid_04;
output [DATA_WIDTH-1:0] dac_data_04;
input dac_enable_05;
input dac_valid_05;
output [DATA_WIDTH-1:0] dac_data_05;
input dac_enable_06;
input dac_valid_06;
output [DATA_WIDTH-1:0] dac_data_06;
input dac_enable_07;
input dac_valid_07;
output [DATA_WIDTH-1:0] dac_data_07;
input fifo_valid;
output dma_rd;
input [NUM_OF_CHANNELS*DATA_WIDTH-1:0] dma_data;
localparam DMA_DATA_WIDTH = NUM_OF_CHANNELS*DATA_WIDTH;
wire [NUM_OF_CHANNELS-1:0] dac_enable;
wire [NUM_OF_CHANNELS-1:0] dac_valid;
wire [DATA_WIDTH-1:0] data_array[0:NUM_OF_CHANNELS-1];
wire [$clog2(NUM_OF_CHANNELS)-1:0] offset [0:NUM_OF_CHANNELS-1];
wire dac_chan_valid;
reg [DATA_WIDTH*NUM_OF_CHANNELS-1:0] dac_data = 'h00;
reg [DMA_DATA_WIDTH-1:0] buffer = 'h00;
reg dma_rd = 1'b0;
reg [$clog2(NUM_OF_CHANNELS)-1:0] rd_counter = 'h00;
reg [$clog2(NUM_OF_CHANNELS)-1:0] req_counter = 'h00;
reg [NUM_OF_CHANNELS-1:0] dac_enable_d1 = 'h00;
assign dac_enable[0] = dac_enable_00;
assign dac_enable[1] = dac_enable_01;
assign dac_enable[2] = dac_enable_02;
assign dac_enable[3] = dac_enable_03;
assign dac_valid[0] = dac_valid_00;
assign dac_valid[1] = dac_valid_01;
assign dac_valid[2] = dac_valid_02;
assign dac_valid[3] = dac_valid_03;
assign dac_data_00 = dac_data[DATA_WIDTH*1-1:DATA_WIDTH*0];
assign dac_data_01 = dac_data[DATA_WIDTH*2-1:DATA_WIDTH*1];
assign dac_data_02 = dac_data[DATA_WIDTH*3-1:DATA_WIDTH*2];
assign dac_data_03 = dac_data[DATA_WIDTH*4-1:DATA_WIDTH*3];
generate
if (NUM_OF_CHANNELS >= 8) begin
assign dac_enable[4] = dac_enable_04;
assign dac_enable[5] = dac_enable_05;
assign dac_enable[6] = dac_enable_06;
assign dac_enable[7] = dac_enable_07;
assign dac_valid[4] = dac_valid_04;
assign dac_valid[5] = dac_valid_05;
assign dac_valid[6] = dac_valid_06;
assign dac_valid[7] = dac_valid_07;
assign dac_data_04 = dac_data[DATA_WIDTH*5-1:DATA_WIDTH*4];
assign dac_data_05 = dac_data[DATA_WIDTH*6-1:DATA_WIDTH*5];
assign dac_data_06 = dac_data[DATA_WIDTH*7-1:DATA_WIDTH*6];
assign dac_data_07 = dac_data[DATA_WIDTH*8-1:DATA_WIDTH*7];
end else begin
assign dac_data_04 = 'h0;
assign dac_data_05 = 'h0;
assign dac_data_06 = 'h0;
assign dac_data_07 = 'h0;
end
endgenerate
function integer enable_reduce;
input n;
integer n;
integer i;
begin
enable_reduce = 0;
for (i = 0; i < n; i = i + 1)
enable_reduce = enable_reduce + dac_enable[i];
end
endfunction
assign dac_chan_valid = |dac_valid;
always @(posedge clk) begin
if (fifo_valid == 1'b1) begin
buffer <= dma_data;
rd_counter <= 'h0;
end else if (dac_chan_valid == 1'b1) begin
rd_counter <= rd_counter + enable_reduce(NUM_OF_CHANNELS);
end
end
always @(posedge clk) begin
dma_rd <= 1'b0;
if (dac_enable != dac_enable_d1) begin
req_counter <= 'h00;
end else if (dac_chan_valid == 1'b1) begin
req_counter <= req_counter + enable_reduce(NUM_OF_CHANNELS);
if (req_counter == 'h00) begin
dma_rd <= 1'b1;
end
end
dac_enable_d1 <= dac_enable;
end
generate
genvar i;
for (i = 0; i < NUM_OF_CHANNELS; i = i + 1) begin : gen_data_array
assign data_array[i] = buffer[DATA_WIDTH+i*DATA_WIDTH-1:i*DATA_WIDTH];
end
endgenerate
generate
genvar j;
for (j = 0; j < NUM_OF_CHANNELS; j = j + 1) begin : gen_dac_data
assign offset[j] = rd_counter + enable_reduce(j);
always @(posedge clk) begin
if (dac_chan_valid) begin
if (dac_enable[j])
dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= data_array[offset[j]];
else
dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= 'h0000;
end
end
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

81
library/util_dac_unpack/util_dac_unpack_hw.tcl
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package require -exact qsys 13.0
source ../scripts/adi_env.tcl
set_module_property NAME util_dac_unpack
set_module_property DESCRIPTION "Util DAC data unpacker"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME util_dac_unpack
set_module_property ELABORATION_CALLBACK util_dac_unpack_elaborate
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL util_dac_unpack
add_fileset_file util_dac_unpack.v VERILOG PATH util_dac_unpack.v
add_parameter NUM_OF_CHANNELS INTEGER 0
set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8
set_parameter_property NUM_OF_CHANNELS ALLOWED_RANGES {4 8}
set_parameter_property NUM_OF_CHANNELS DESCRIPTION "Valid values are 4 and 8"
set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS
set_parameter_property NUM_OF_CHANNELS TYPE INTEGER
set_parameter_property NUM_OF_CHANNELS UNITS None
set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true
add_parameter DATA_WIDTH INTEGER 0
set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
set_parameter_property DATA_WIDTH TYPE INTEGER
set_parameter_property DATA_WIDTH UNITS None
set_parameter_property DATA_WIDTH HDL_PARAMETER true
add_interface data_clock clock end
add_interface_port data_clock clk clk Input 1
proc util_dac_unpack_elaborate {} {
set DW [ get_parameter_value DATA_WIDTH ]
set CHAN [ get_parameter_value NUM_OF_CHANNELS ]
add_interface channels_data conduit end
set_interface_property channels_data associatedClock data_clock
add_interface_port channels_data dac_enable_00 dac_enable_00 Input 1
add_interface_port channels_data dac_valid_00 dac_valid_00 Input 1
add_interface_port channels_data dac_data_00 dac_data_00 Output DATA_WIDTH
add_interface_port channels_data dac_enable_01 dac_enable_01 Input 1
add_interface_port channels_data dac_valid_01 dac_valid_01 Input 1
add_interface_port channels_data dac_data_01 dac_data_01 Output DATA_WIDTH
add_interface_port channels_data dac_enable_02 dac_enable_02 Input 1
add_interface_port channels_data dac_valid_02 dac_valid_02 Input 1
add_interface_port channels_data dac_data_02 dac_data_02 Output DATA_WIDTH
add_interface_port channels_data dac_enable_03 dac_enable_03 Input 1
add_interface_port channels_data dac_valid_03 dac_valid_03 Input 1
add_interface_port channels_data dac_data_03 dac_data_03 Output DATA_WIDTH
if {$CHAN == 8} {
add_interface_port channels_data dac_enable_04 dac_enable_04 Input 1
add_interface_port channels_data dac_valid_04 dac_valid_04 Input 1
add_interface_port channels_data dac_data_04 dac_data_04 Output DATA_WIDTH
add_interface_port channels_data dac_enable_05 dac_enable_05 Input 1
add_interface_port channels_data dac_valid_05 dac_valid_05 Input 1
add_interface_port channels_data dac_data_05 dac_data_05 Output DATA_WIDTH
add_interface_port channels_data dac_enable_06 dac_enable_06 Input 1
add_interface_port channels_data dac_valid_06 dac_valid_06 Input 1
add_interface_port channels_data dac_data_06 dac_data_06 Output DATA_WIDTH
add_interface_port channels_data dac_enable_07 dac_enable_07 Input 1
add_interface_port channels_data dac_valid_07 dac_valid_07 Input 1
add_interface_port channels_data dac_data_07 dac_data_07 Output DATA_WIDTH
}
add_interface_port channels_data fifo_valid fifo_valid Input 1
add_interface_port channels_data dma_rd dma_rd Output 1
add_interface_port channels_data dma_data dma_data Input [expr {$DW * $CHAN}]
}

46
library/util_dac_unpack/util_dac_unpack_ip.tcl
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_dac_unpack
adi_ip_files util_dac_unpack [list \
"util_dac_unpack.v" ]
adi_ip_properties_lite util_dac_unpack
ipx::remove_bus_interface {s} [ipx::current_core]
ipx::remove_bus_interface {m} [ipx::current_core]
ipx::remove_bus_interface {fifo} [ipx::current_core]
ipx::remove_bus_interface {signal_clock} [ipx::current_core]
ipx::remove_memory_map {m} [ipx::current_core]
ipx::remove_address_space {s} [ipx::current_core]
ipx::remove_address_space {fifo} [ipx::current_core]
for {set i 0} {$i < 8} {incr i} {
foreach port {"dac_enable" "dac_valid" "dac_data"} {
set name [format "%s_%.2d" $port $i]
set_property ENABLEMENT_DEPENDENCY \
"(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i)" \
[ipx::get_ports $name]
}
foreach port {"dac_enable" "dac_valid"} {
set name [format "%s_%.2d" $port $i]
set_property DRIVER_VALUE "0" [ipx::get_ports $name]
}
}
adi_add_bus "fifo_rd" "master" \
"analog.com:interface:fifo_rd_rtl:1.0" \
"analog.com:interface:fifo_rd:1.0" \
{ \
{"dma_rd" "EN"} \
{"dma_data" "DATA"} \
{"fifo_valid" "VALID"} \
}
adi_add_bus_clock "clk" "fifo_rd"
ipx::save_core [ipx::current_core]