ad_dds_2: Remove unused disable logic feature
parent
8a306ce96b
commit
892febe68a
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@ -87,13 +87,7 @@ module ad_dds_2 #(
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wire [DDS_P_DW-1:0] dds_phase_0_s;
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wire [DDS_P_DW-1:0] dds_phase_0_s;
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wire [DDS_P_DW-1:0] dds_phase_1_s;
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wire [DDS_P_DW-1:0] dds_phase_1_s;
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// disable DDS
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generate
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generate
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if (DISABLE == 1) begin
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// assign 0 for the exact buss width to avoid warnings
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assign dds_data = {DDS_DW{1'b0}};
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end else begin
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// dds channel output
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// dds channel output
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assign dds_data = dds_data_out;
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assign dds_data = dds_data_out;
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@ -125,20 +119,20 @@ module ad_dds_2 #(
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end
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end
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// phase
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// phase
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if (DDS_P_DW >= PHASE_DW) begin
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if (DDS_P_DW > PHASE_DW) begin
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assign dds_phase_0_s = {dds_phase_0,{DDS_P_DW-(PHASE_DW-1){1'b0}}};
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assign dds_phase_0_s = {dds_phase_0,{DDS_P_DW-PHASE_DW{1'b0}}};
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assign dds_phase_1_s = {dds_phase_1,{DDS_P_DW-(PHASE_DW-1){1'b0}}};
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assign dds_phase_1_s = {dds_phase_1,{DDS_P_DW-PHASE_DW{1'b0}}};
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end else begin
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end else begin
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assign dds_phase_0_s = {dds_phase_0[(PHASE_DW-1):PHASE_DW-DDS_P_DW],1'b0};
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assign dds_phase_0_s = dds_phase_0[(PHASE_DW-1):PHASE_DW-DDS_P_DW];
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assign dds_phase_1_s = {dds_phase_1[(PHASE_DW-1):PHASE_DW-DDS_P_DW],1'b0};
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assign dds_phase_1_s = dds_phase_1[(PHASE_DW-1):PHASE_DW-DDS_P_DW];
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end
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end
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// dds-1
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// dds-1
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ad_dds_1 #(
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ad_dds_1 #(
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.DDS_TYPE(DDS_TYPE),
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.DDS_TYPE(DDS_TYPE),
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.DDS_D_DW(CORDIC_DW),
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.DDS_D_DW(DDS_D_DW),
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.DDS_P_DW(CORDIC_PHASE_DW))
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.DDS_P_DW(DDS_P_DW))
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i_dds_1_0 (
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i_dds_1_0 (
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.clk (clk),
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.clk (clk),
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.angle (dds_phase_0_s),
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.angle (dds_phase_0_s),
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@ -156,7 +150,6 @@ module ad_dds_2 #(
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.angle (dds_phase_1_s),
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.angle (dds_phase_1_s),
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.scale (dds_scale_1_d),
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.scale (dds_scale_1_d),
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.dds_data (dds_data_1_s));
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.dds_data (dds_data_1_s));
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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