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usdrx1: Update project so that the AD9671 cores can be synchronized

main
Adrian Costina 2014-10-13 17:06:40 +03:00
parent f528873fa9
commit 8934a66013
6 changed files with 111 additions and 21 deletions
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10
library/axi_ad9671/axi_ad9671.v
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@ -56,6 +56,8 @@ module axi_ad9671 (
adc_data,
adc_dovf,
adc_dunf,
adc_raddr_in,
adc_raddr_out,
// axi interface
@ -102,6 +104,8 @@ module axi_ad9671 (
output [127:0] adc_data;
input adc_dovf;
input adc_dunf;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
// axi interface
@ -190,7 +194,7 @@ module axi_ad9671 (
// main (device interface)
axi_ad9671_if #(.PCORE_4L_2L_N(PCORE_4L_2L_N)) i_if (
axi_ad9671_if #(.PCORE_4L_2L_N(PCORE_4L_2L_N), .PCORE_ID(PCORE_ID)) i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.rx_data_sof (rx_data_sof),
@ -213,7 +217,9 @@ module axi_ad9671 (
.adc_or_g (adc_or_s[6]),
.adc_data_h (adc_data_s[7]),
.adc_or_h (adc_or_s[7]),
.adc_status (adc_status_s));
.adc_status (adc_status_s),
.adc_raddr_in(adc_raddr_in),
.adc_raddr_out(adc_raddr_out));
// channels

3
library/axi_ad9671/axi_ad9671_hw.tcl
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@ -1,6 +1,6 @@
package require -exact qsys 13.0
package require -exact qsys 14.0
source ../scripts/adi_env.tcl
set_module_property NAME axi_ad9671
@ -23,6 +23,7 @@ add_fileset_file up_drp_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up
add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
add_fileset_file axi_ad9671_pnmon.v VERILOG PATH axi_ad9671_pnmon.v
add_fileset_file axi_ad9671_if.v VERILOG PATH axi_ad9671_if.v
add_fileset_file axi_ad9671_channel.v VERILOG PATH axi_ad9671_channel.v

96
library/axi_ad9671/axi_ad9671_if.v
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@ -70,11 +70,14 @@ module axi_ad9671_if (
adc_or_g,
adc_data_h,
adc_or_h,
adc_status);
adc_status,
adc_raddr_in,
adc_raddr_out);
// parameters
parameter PCORE_4L_2L_N = 1;
parameter PCORE_ID = 0;
// jesd interface
// rx_clk is (line-rate/40)
@ -105,17 +108,45 @@ module axi_ad9671_if (
output [ 15:0] adc_data_h;
output adc_or_h;
output adc_status;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
// internal wires
wire [127:0] adc_wdata;
wire [127:0] adc_rdata;
wire [ 15:0] adc_data_a_s;
wire [ 15:0] adc_data_b_s;
wire [ 15:0] adc_data_c_s;
wire [ 15:0] adc_data_d_s;
wire [ 15:0] adc_data_e_s;
wire [ 15:0] adc_data_f_s;
wire [ 15:0] adc_data_g_s;
wire [ 15:0] adc_data_h_s;
wire [ 3:0] adc_raddr_s;
// internal registers
reg int_valid = 'd0;
reg [127:0] int_data = 'd0;
reg adc_status = 'd0;
reg adc_start = 'd0;
reg [ 3:0] adc_waddr = 'd0;
reg [ 3:0] adc_raddr_out = 'd0;
reg [ 15:0] adc_data_a;
reg [ 15:0] adc_data_b;
reg [ 15:0] adc_data_c;
reg [ 15:0] adc_data_d;
reg [ 15:0] adc_data_e;
reg [ 15:0] adc_data_f;
reg [ 15:0] adc_data_g;
reg [ 15:0] adc_data_h;
// adc clock & valid
assign adc_clk = rx_clk;
assign adc_valid = int_valid;
assign adc_valid = int_valid & adc_start;
assign adc_or_a = 'd0;
assign adc_or_b = 'd0;
@ -125,15 +156,49 @@ module axi_ad9671_if (
assign adc_or_f = 'd0;
assign adc_or_g = 'd0;
assign adc_or_h = 'd0;
assign adc_data_a = {int_data[ 7: 0], int_data[ 15: 8]};
assign adc_data_b = {int_data[ 23: 16], int_data[ 31: 24]};
assign adc_data_c = {int_data[ 39: 32], int_data[ 47: 40]};
assign adc_data_d = {int_data[ 55: 48], int_data[ 63: 56]};
assign adc_data_e = {int_data[ 71: 64], int_data[ 79: 72]};
assign adc_data_f = {int_data[ 87: 80], int_data[ 95: 88]};
assign adc_data_g = {int_data[103: 96], int_data[111:104]};
assign adc_data_h = {int_data[119:112], int_data[127:120]};
assign adc_data_a_s = {int_data[ 7: 0], int_data[ 15: 8]};
assign adc_data_b_s = {int_data[ 23: 16], int_data[ 31: 24]};
assign adc_data_c_s = {int_data[ 39: 32], int_data[ 47: 40]};
assign adc_data_d_s = {int_data[ 55: 48], int_data[ 63: 56]};
assign adc_data_e_s = {int_data[ 71: 64], int_data[ 79: 72]};
assign adc_data_f_s = {int_data[ 87: 80], int_data[ 95: 88]};
assign adc_data_g_s = {int_data[103: 96], int_data[111:104]};
assign adc_data_h_s = {int_data[119:112], int_data[127:120]};
assign adc_wdata = {adc_data_h_s, adc_data_g_s, adc_data_f_s, adc_data_e_s,
adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s};
assign adc_raddr_s = (PCORE_ID == 0) ? adc_raddr_out : adc_raddr_in;
always @(posedge rx_clk)
begin
adc_data_a <= adc_rdata[ 15: 0];
adc_data_b <= adc_rdata[ 31: 16];
adc_data_c <= adc_rdata[ 47: 32];
adc_data_d <= adc_rdata[ 63: 48];
adc_data_e <= adc_rdata[ 79: 64];
adc_data_f <= adc_rdata[ 95: 80];
adc_data_g <= adc_rdata[111: 96];
adc_data_h <= adc_rdata[127:112];
end
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8;
adc_start <= 1'b0;
end
else begin
if (int_valid == 1'b1 && adc_data_a_s == 16'hbeef) begin
adc_start <= 1'b1;
end
if (int_valid == 1'b1 && adc_start == 1'b1) begin
adc_waddr <= adc_waddr + 1;
adc_raddr_out <= adc_raddr_out + 1;
end
end
end
always @(posedge rx_clk) begin
if (PCORE_4L_2L_N == 1'b1) begin
@ -154,6 +219,15 @@ module axi_ad9671_if (
end
end
ad_mem #(.ADDR_WIDTH(4), .DATA_WIDTH(128)) i_mem (
.clka(rx_clk),
.wea(int_valid),
.addra(adc_waddr),
.dina(adc_wdata),
.clkb(rx_clk),
.addrb(adc_raddr_s),
.doutb(adc_rdata));
endmodule
// ***************************************************************************

1
library/axi_ad9671/axi_ad9671_ip.tcl
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@ -16,6 +16,7 @@ adi_ip_files axi_ad9671 [list \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_mem.v" \
"axi_ad9671_pnmon.v" \
"axi_ad9671_channel.v" \
"axi_ad9671_if.v" \

6
projects/usdrx1/a5gt/system_top.v
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@ -317,7 +317,7 @@ module system_top (
sld_signaltap #(
.sld_advanced_trigger_entity ("basic,1,"),
.sld_data_bits (258),
.sld_data_bits (514),
.sld_data_bit_cntr_bits (8),
.sld_enable_advanced_trigger (0),
.sld_mem_address_bits (10),
@ -334,8 +334,8 @@ module system_top (
.sld_trigger_level (1),
.sld_trigger_level_pipeline (1))
i_signaltap (
.acq_clk (rx_clk),
.acq_data_in ({rx_sysref, rx_sync, rx_ip_data_s}),
.acq_clk (adc_clk),
.acq_data_in ({rx_sysref, rx_sync, dma_data}),
.acq_trigger_in ({rx_sysref, rx_sync}));
genvar n;

16
projects/usdrx1/common/usdrx1_bd.tcl
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@ -48,16 +48,20 @@ set adc_dovf [create_bd_port -dir O adc_dovf]
# adc peripherals
set axi_ad9671_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_0]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_0]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] $axi_ad9671_core_0
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9671_core_0
set axi_ad9671_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_1]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_1]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] $axi_ad9671_core_1
set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9671_core_1
set axi_ad9671_core_2 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_2]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_2]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] $axi_ad9671_core_2
set_property -dict [list CONFIG.PCORE_ID {2}] $axi_ad9671_core_2
set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_3]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_3]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] $axi_ad9671_core_3
set_property -dict [list CONFIG.PCORE_ID {3}] $axi_ad9671_core_3
set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_usdrx1_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd
@ -190,6 +194,10 @@ connect_bd_net -net axi_ad9671_dma_wr_en [get_bd_pins axi_usdrx1_dma/
connect_bd_net -net axi_ad9671_dma_adc_data [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_data]
connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf]
connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_0/adc_raddr_out]
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_1/adc_raddr_in]
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_2/adc_raddr_in]
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_3/adc_raddr_in]
# interconnect (cpu)