diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl index 704813c12..757783157 100644 --- a/projects/daq1/common/daq1_bd.tcl +++ b/projects/daq1/common/daq1_bd.tcl @@ -15,6 +15,16 @@ set rx_sysref [create_bd_port -dir I rx_sysref] set rx_data_p [create_bd_port -dir I -from 1 -to 0 rx_data_p] set rx_data_n [create_bd_port -dir I -from 1 -to 0 rx_data_n] +set dac_clk [create_bd_port -dir O dac_clk] +set dac_valid_0 [create_bd_port -dir O dac_valid_0] +set dac_enable_0 [create_bd_port -dir O dac_enable_0] +set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0] +set dac_valid_1 [create_bd_port -dir O dac_valid_1] +set dac_enable_1 [create_bd_port -dir O dac_enable_1] +set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1] +set dac_drd [create_bd_port -dir I dac_drd] +set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata] + set adc_clk [create_bd_port -dir O adc_clk] set adc_enable_a [create_bd_port -dir O adc_enable_a] set adc_valid_a [create_bd_port -dir O adc_valid_a] @@ -22,9 +32,9 @@ set adc_data_a [create_bd_port -dir O -from 31 -to 0 adc_data_a] set adc_enable_b [create_bd_port -dir O adc_enable_b] set adc_valid_b [create_bd_port -dir O adc_valid_b] set adc_data_b [create_bd_port -dir O -from 31 -to 0 adc_data_b] -set dma_wr [create_bd_port -dir I dma_wr] -set dma_sync [create_bd_port -dir I dma_sync] -set dma_data [create_bd_port -dir I -from 63 -to 0 dma_data] +set adc_dwr [create_bd_port -dir I adc_dwr] +set adc_dsync [create_bd_port -dir I adc_dsync] +set adc_ddata [create_bd_port -dir I -from 63 -to 0 adc_ddata] set tx_ref_clk_p [create_bd_port -dir I tx_ref_clk_p] set tx_ref_clk_n [create_bd_port -dir I tx_ref_clk_n] @@ -136,6 +146,7 @@ connect_bd_net -net axi_daq1_gt_rx_sync [get_bd_pins axi_daq1_gt/rx_sy connect_bd_net -net axi_daq1_gt_rx_ext_sysref [get_bd_pins axi_daq1_gt/rx_ext_sysref] [get_bd_ports rx_sysref] # connections (adc) + connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_daq1_gt/rx_clk_g] connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_daq1_gt/rx_clk] connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_ad9250_core/rx_clk] @@ -153,18 +164,21 @@ connect_bd_net -net axi_daq1_gt_rx_ip_sync [get_bd_pins axi_daq1_gt/rx_ip connect_bd_net -net axi_daq1_gt_rx_ip_sof [get_bd_pins axi_daq1_gt/rx_ip_sof] [get_bd_pins axi_ad9250_jesd/rx_start_of_frame] connect_bd_net -net axi_daq1_gt_rx_ip_data [get_bd_pins axi_daq1_gt/rx_ip_data] [get_bd_pins axi_ad9250_jesd/rx_tdata] connect_bd_net -net axi_daq1_gt_rx_data [get_bd_pins axi_daq1_gt/rx_data] [get_bd_pins axi_ad9250_core/rx_data] -connect_bd_net -net axi_ad9250_adc_clk [get_bd_pins axi_ad9250_core/adc_clk] [get_bd_pins axi_ad9250_dma/fifo_wr_clk] [get_bd_ports adc_clk] +connect_bd_net -net axi_ad9250_adc_clk [get_bd_pins axi_ad9250_core/adc_clk] [get_bd_pins axi_ad9250_dma/fifo_wr_clk] connect_bd_net -net axi_ad9250_adc_enable_a [get_bd_pins axi_ad9250_core/adc_enable_a] [get_bd_ports adc_enable_a] connect_bd_net -net axi_ad9250_adc_valid_a [get_bd_pins axi_ad9250_core/adc_valid_a] [get_bd_ports adc_valid_a] connect_bd_net -net axi_ad9250_adc_data_a [get_bd_pins axi_ad9250_core/adc_data_a] [get_bd_ports adc_data_a] connect_bd_net -net axi_ad9250_adc_enable_b [get_bd_pins axi_ad9250_core/adc_enable_b] [get_bd_ports adc_enable_b] connect_bd_net -net axi_ad9250_adc_valid_b [get_bd_pins axi_ad9250_core/adc_valid_b] [get_bd_ports adc_valid_b] connect_bd_net -net axi_ad9250_adc_data_b [get_bd_pins axi_ad9250_core/adc_data_b] [get_bd_ports adc_data_b] -connect_bd_net -net axi_ad9250_dma_wr [get_bd_pins axi_ad9250_dma/fifo_wr_en] [get_bd_ports dma_wr] -connect_bd_net -net axi_ad9250_dma_sync [get_bd_pins axi_ad9250_dma/fifo_wr_sync] [get_bd_ports dma_sync] -connect_bd_net -net axi_ad9250_dma_data [get_bd_pins axi_ad9250_dma/fifo_wr_din] [get_bd_ports dma_data] +connect_bd_net -net axi_ad9250_adc_dovf [get_bd_pins axi_ad9250_core/adc_dovf] [get_bd_pins axi_ad9250_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad9250_dma_wr [get_bd_pins axi_ad9250_dma/fifo_wr_en] [get_bd_ports adc_dwr] +connect_bd_net -net axi_ad9250_dma_sync [get_bd_pins axi_ad9250_dma/fifo_wr_sync] [get_bd_ports adc_dsync] +connect_bd_net -net axi_ad9250_dma_data [get_bd_pins axi_ad9250_dma/fifo_wr_din] [get_bd_ports adc_ddata] connect_bd_net -net axi_ad9250_dma_irq [get_bd_pins axi_ad9250_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_ad9250_adc_clk [get_bd_ports adc_clk] + # connections (dac) connect_bd_net -net axi_ad9122_dac_clk_in_p [get_bd_pins axi_ad9122_core/dac_clk_in_p] [get_bd_ports tx_ref_clk_p] @@ -176,11 +190,19 @@ connect_bd_net -net axi_ad9122_dac_frame_out_n [get_bd_pins axi_ad9122_core/d connect_bd_net -net axi_ad9122_dac_data_out_p [get_bd_pins axi_ad9122_core/dac_data_out_p] [get_bd_ports tx_data_p] connect_bd_net -net axi_ad9122_dac_data_out_n [get_bd_pins axi_ad9122_core/dac_data_out_n] [get_bd_ports tx_data_n] connect_bd_net -net axi_ad9122_dac_div_clk [get_bd_pins axi_ad9122_core/dac_div_clk] [get_bd_pins axi_ad9122_dma/fifo_rd_clk] -connect_bd_net -net axi_ad9122_dac_drd [get_bd_pins axi_ad9122_core/dac_drd] [get_bd_pins axi_ad9122_dma/fifo_rd_en] -connect_bd_net -net axi_ad9122_dac_ddata [get_bd_pins axi_ad9122_core/dac_ddata] [get_bd_pins axi_ad9122_dma/fifo_rd_dout] +connect_bd_net -net axi_ad9122_dac_valid_0 [get_bd_pins axi_ad9122_core/dac_valid_0] [get_bd_ports dac_valid_0] +connect_bd_net -net axi_ad9122_dac_enable_0 [get_bd_pins axi_ad9122_core/dac_enable_0] [get_bd_ports dac_enable_0] +connect_bd_net -net axi_ad9122_dac_ddata_0 [get_bd_pins axi_ad9122_core/dac_ddata_0] [get_bd_ports dac_ddata_0] +connect_bd_net -net axi_ad9122_dac_valid_1 [get_bd_pins axi_ad9122_core/dac_valid_1] [get_bd_ports dac_valid_1] +connect_bd_net -net axi_ad9122_dac_enable_1 [get_bd_pins axi_ad9122_core/dac_enable_1] [get_bd_ports dac_enable_1] +connect_bd_net -net axi_ad9122_dac_ddata_1 [get_bd_pins axi_ad9122_core/dac_ddata_1] [get_bd_ports dac_ddata_1] +connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_drd] +connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_ddata] connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122_core/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow] connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3] +connect_bd_net -net axi_ad9122_dac_div_clk [get_bd_ports dac_clk] + # interconnect (cpu) connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9122_dma/s_axi] diff --git a/projects/daq1/zc706/system_top.v b/projects/daq1/zc706/system_top.v index 50d3ba9fe..c5e0a20cf 100644 --- a/projects/daq1/zc706/system_top.v +++ b/projects/daq1/zc706/system_top.v @@ -180,57 +180,94 @@ module system_top ( inout spi_sdio; // internal registers - reg dma_wr = 'd0; - reg [63:0] dma_data = 'd0; + + reg dac_drd = 'd0; + reg [63:0] dac_ddata_0 = 'd0; + reg [63:0] dac_ddata_1 = 'd0; + reg adc_dwr = 'd0; + reg [63:0] adc_ddata = 'd0; // internal signals wire [39:0] gpio_i; wire [39:0] gpio_o; wire [39:0] gpio_t; - wire rx_ref_clk; wire rx_sysref; wire rx_sync; wire [ 2:0] spi_csn; - wire adc_clk; - wire adc_enable_a; wire [31:0] adc_data_a; - wire adc_enable_b; wire [31:0] adc_data_b; + wire adc_enable_a; + wire adc_enable_b; + wire dac_clk; + wire [127:0] dac_ddata; + wire dac_enable_0; + wire dac_enable_1; // pack & unpack data + always @(posedge dac_clk) begin + case ({dac_enable_1, dac_enable_0}) + 2'b11: begin + dac_drd <= 1'b1; + dac_ddata_1[63:48] <= dac_ddata[127:112]; + dac_ddata_1[47:32] <= dac_ddata[ 95: 80]; + dac_ddata_1[31:16] <= dac_ddata[ 63: 48]; + dac_ddata_1[15: 0] <= dac_ddata[ 31: 16]; + dac_ddata_0[63:48] <= dac_ddata[111: 96]; + dac_ddata_0[47:32] <= dac_ddata[ 79: 64]; + dac_ddata_0[31:16] <= dac_ddata[ 47: 32]; + dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; + end + 2'b01: begin + dac_drd <= ~dac_drd; + dac_ddata_1 <= 64'd0; + dac_ddata_0 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0]; + end + 2'b10: begin + dac_drd <= ~dac_drd; + dac_ddata_1 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0]; + dac_ddata_0 <= 64'd0; + end + default: begin + dac_drd <= 1'b0; + dac_ddata_1 <= 64'd0; + dac_ddata_0 <= 64'd0; + end + endcase + end + always @(posedge adc_clk) begin case ({adc_enable_b, adc_enable_a}) 2'b11: begin - dma_wr <= 1'b1; - dma_data[63:48] <= adc_data_b[31:16]; - dma_data[47:32] <= adc_data_a[31:16]; - dma_data[31:16] <= adc_data_b[15: 0]; - dma_data[15: 0] <= adc_data_a[15: 0]; + adc_dwr <= 1'b1; + adc_ddata[63:48] <= adc_data_b[31:16]; + adc_ddata[47:32] <= adc_data_a[31:16]; + adc_ddata[31:16] <= adc_data_b[15: 0]; + adc_ddata[15: 0] <= adc_data_a[15: 0]; end 2'b10: begin - dma_wr <= ~dma_wr; - dma_data[63:48] <= adc_data_b[31:16]; - dma_data[47:32] <= adc_data_b[15: 0]; - dma_data[31:16] <= dma_data[63:48]; - dma_data[15: 0] <= dma_data[47:32]; + adc_dwr <= ~adc_dwr; + adc_ddata[63:48] <= adc_data_b[31:16]; + adc_ddata[47:32] <= adc_data_b[15: 0]; + adc_ddata[31:16] <= adc_ddata[63:48]; + adc_ddata[15: 0] <= adc_ddata[47:32]; end 2'b01: begin - dma_wr <= ~dma_wr; - dma_data[63:48] <= adc_data_a[31:16]; - dma_data[47:32] <= adc_data_a[15: 0]; - dma_data[31:16] <= dma_data[63:48]; - dma_data[15: 0] <= dma_data[47:32]; + adc_dwr <= ~adc_dwr; + adc_ddata[63:48] <= adc_data_a[31:16]; + adc_ddata[47:32] <= adc_data_a[15: 0]; + adc_ddata[31:16] <= adc_ddata[63:48]; + adc_ddata[15: 0] <= adc_ddata[47:32]; end default: begin - dma_wr <= 1'b0; - dma_data[63:48] <= 16'd0; - dma_data[47:32] <= 16'd0; - dma_data[31:16] <= 16'd0; - dma_data[15: 0] <= 16'd0; + adc_dwr <= 1'b0; + adc_ddata[63:48] <= 16'd0; + adc_ddata[47:32] <= 16'd0; + adc_ddata[31:16] <= 16'd0; + adc_ddata[15: 0] <= 16'd0; end endcase end @@ -305,6 +342,25 @@ module system_top ( .GPIO_I (gpio_i), .GPIO_O (gpio_o), .GPIO_T (gpio_t), + .adc_clk (adc_clk), + .adc_data_a (adc_data_a), + .adc_data_b (adc_data_b), + .adc_ddata (adc_ddata), + .adc_dsync (1'b1), + .adc_dwr (adc_dwr), + .adc_enable_a (adc_enable_a), + .adc_enable_b (adc_enable_b), + .adc_valid_a (), + .adc_valid_b (), + .dac_clk (dac_clk), + .dac_ddata (dac_ddata), + .dac_ddata_0 (dac_ddata_0), + .dac_ddata_1 (dac_ddata_1), + .dac_drd (dac_drd), + .dac_enable_0 (dac_enable_0), + .dac_enable_1 (dac_enable_1), + .dac_valid_0 (), + .dac_valid_1 (), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -317,16 +373,6 @@ module system_top ( .rx_ref_clk (rx_ref_clk), .rx_sync (rx_sync), .rx_sysref (rx_sysref), - .adc_clk (adc_clk), - .adc_data_a (adc_data_a), - .adc_data_b (adc_data_b), - .adc_enable_a (adc_enable_a), - .adc_enable_b (adc_enable_b), - .adc_valid_a (), - .adc_valid_b (), - .dma_data (dma_data), - .dma_sync (1'b1), - .dma_wr (dma_wr), .spdif (spdif), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk),