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axi_adxcvr: Fix warning related to up_es_reset 

Fix the following warning:

WARNING: [Synth 8-2611] redeclaration of ANSI port up_es_reset is not allowed

Also make sure, that in all configurations, the register has a diver.
main
Istvan Csomortani 2019-03-20 15:26:46 +00:00 committed by István Csomortáni
parent 59713f96ab
commit 8996044978
1 changed files with 3 additions and 2 deletions
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5
library/xilinx/axi_adxcvr/axi_adxcvr_up.v
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@ -87,7 +87,7 @@ module axi_adxcvr_up #(
output [ 7:0] up_es_sel, output [ 7:0] up_es_sel,
output up_es_req, output up_es_req,
output [15:0] up_es_reset, output reg [15:0] up_es_reset,
input up_es_ack, input up_es_ack,
output [ 4:0] up_es_pscale, output [ 4:0] up_es_pscale,
output [ 1:0] up_es_vrange, output [ 1:0] up_es_vrange,
@ -164,7 +164,6 @@ module axi_adxcvr_up #(
reg up_ies_status = 'd0; reg up_ies_status = 'd0;
reg up_rreq_d = 'd0; reg up_rreq_d = 'd0;
reg [31:0] up_rdata_d = 'd0; reg [31:0] up_rdata_d = 'd0;
reg [15:0] up_es_reset = 'd0;
// internal signals // internal signals
@ -395,6 +394,7 @@ module axi_adxcvr_up #(
up_ies_hoffset_step <= 'd0; up_ies_hoffset_step <= 'd0;
up_ies_start_addr <= 'd0; up_ies_start_addr <= 'd0;
up_ies_status <= 'd0; up_ies_status <= 'd0;
up_es_reset <= 'd0;
end else begin end else begin
up_ies_sel <= 'd0; up_ies_sel <= 'd0;
up_ies_req <= 'd0; up_ies_req <= 'd0;
@ -408,6 +408,7 @@ module axi_adxcvr_up #(
up_ies_hoffset_step <= 'd0; up_ies_hoffset_step <= 'd0;
up_ies_start_addr <= 'd0; up_ies_start_addr <= 'd0;
up_ies_status <= 'd0; up_ies_status <= 'd0;
up_es_reset <= 'd0;
end end
end end
end else begin end else begin