prcfg_lib: Update the PR libraries

+ Flop the control nets too inside the adc/dac module
  + Flop the gpio_out in prcfg_top

library/prcfg/bist/prcfg_adc.v

@@ -77,6 +77,11 @@ module prcfg_adc (
   output  [31:0]    dst_adc_ddata;
   input             dst_adc_dovf;
 
+  reg               dst_adc_dwr;
+  reg               dst_adc_dsync;
+  reg     [31:0]    dst_adc_ddata;
+  reg               src_adc_dovf;
+
   reg     [31:0]    status            = 0;
   reg     [31:0]    adc_pn_data       = 0;
   reg               adc_dvalid_d      = 0;
@@ -170,11 +175,12 @@ module prcfg_adc (
   end
 
   // rx path are passed through on test mode
-  assign dst_adc_dwr    = src_adc_dwr;
-  assign dst_adc_dsync  = src_adc_dsync;
-  assign dst_adc_ddata  = src_adc_ddata;
-  assign src_adc_dovf   = dst_adc_dovf;
-
+  always @(posedge clk) begin
+    dst_adc_dwr    <= src_adc_dwr;
+    dst_adc_dsync  <= src_adc_dsync;
+    dst_adc_ddata  <= src_adc_ddata;
+    src_adc_dovf   <= dst_adc_dovf;
+  end
   // setup status bits for gpio_out
   always @(posedge clk) begin
     if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin

library/prcfg/common/prcfg_top.v

@@ -101,6 +101,8 @@ module prcfg_top(
   output  [(DBUS_WIDTH - 1):0]      dma_adc_ddata;
   input                             dma_adc_ovf;
 
+  reg     [31:0]                    gpio_output;
+
   wire    [31:0]                    adc_status_s[(NUM_CHANNEL - 1):0];
   wire    [31:0]                    dac_status_s[(NUM_CHANNEL - 1):0];
 
@@ -174,8 +176,9 @@ module prcfg_top(
           );
         end
       end
-
-      assign gpio_output = gpio_output | adc_status_s[l_inst] | dac_status_s[l_inst];
+      always @(posedge clk) begin
+        gpio_output <= gpio_output | adc_status_s[l_inst] | dac_status_s[l_inst];
+      end
     end
   endgenerate
 

library/prcfg/default/prcfg_adc.v

@@ -77,11 +77,17 @@ module prcfg_adc (
   output  [31:0]    dst_adc_ddata;
   input             dst_adc_dovf;
 
+  reg               dst_adc_dwr;
+  reg               dst_adc_dsync;
+  reg     [31:0]    dst_adc_ddata;
+  reg               src_adc_dovf;
+
   assign status = {24'h0, RP_ID};
 
-  assign dst_adc_dwr    = src_adc_dwr;
-  assign dst_adc_dsync  = src_adc_dsync;
-  assign dst_adc_ddata  = src_adc_ddata;
-  assign src_adc_dovf   = dst_adc_dovf;
-
+  always @(posedge clk) begin
+    dst_adc_dwr    <= src_adc_dwr;
+    dst_adc_dsync  <= src_adc_dsync;
+    dst_adc_ddata  <= src_adc_ddata;
+    src_adc_dovf   <= dst_adc_dovf;
+  end
 endmodule

library/prcfg/default/prcfg_dac.v

@@ -74,10 +74,15 @@ module prcfg_dac(
   output  [31:0]    dst_dac_ddata;
   output            dst_dac_dunf;
 
+  reg               src_dac_drd;
+  reg     [31:0]    dst_dac_ddata;
+  reg               dst_dac_dunf;
+
   assign status = {24'h0, RP_ID};
 
-  assign src_dac_drd    = dst_dac_drd;
-  assign dst_dac_ddata  = src_dac_ddata;
-  assign dst_dac_dunf   = src_dac_dunf;
-
+  always @(posedge clk) begin
+    src_dac_drd    <= dst_dac_drd;
+    dst_dac_ddata  <= src_dac_ddata;
+    dst_dac_dunf   <= src_dac_dunf;
+  end
 endmodule

library/prcfg/qpsk/prcfg_adc.v

@@ -77,6 +77,10 @@ module prcfg_adc (
   output  [31:0]    dst_adc_ddata;
   input             dst_adc_dovf;
 
+  reg               src_adc_dovf;
+  reg               dst_adc_dwr;
+  reg               dst_adc_dsync;
+
   reg     [31:0]    dst_adc_ddata     = 0;
   reg     [31:0]    status            = 0;
   reg     [ 7:0]    adc_pn_data       = 0;
@@ -155,13 +159,13 @@ module prcfg_adc (
     .data_output(adc_ddata_s)
   );
 
-  // output logic for rx side
-  assign src_adc_dovf   = dst_adc_dovf;
-  assign dst_adc_dwr    = src_adc_dwr;
-  assign dst_adc_dsync  = src_adc_dsync;
-
   // output logic for data ans status
   always @(posedge clk) begin
+
+    src_adc_dovf   <= dst_adc_dovf;
+    dst_adc_dwr    <= src_adc_dwr;
+    dst_adc_dsync  <= src_adc_dsync;
+
     if(mode == 0) begin
       dst_adc_ddata <= src_adc_ddata;
     end else begin