fmcomms1: Updated project to vivado 2014.2
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041d8faaf7
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@ -241,7 +241,8 @@ if {$sys_zynq == 0 } {
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# ila (adc)
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set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc]
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set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_adc]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_adc
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@ -249,8 +250,8 @@ if {$sys_zynq == 0 } {
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set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
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connect_bd_net -net sys_200m_clk [get_bd_pins ila_adc/clk]
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connect_bd_net -net axi_ad9643_dma_dwr [get_bd_pins ila_adc/probe0]
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connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins ila_adc/probe1]
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connect_bd_net -net axi_ad9643_dma_dwr [get_bd_pins ila_adc/PROBE0]
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connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins ila_adc/PROBE1]
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# reference clock
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