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axi_dmac: Move m_axi_src interface clock and reset next to other signals 

Move the clock and reset signals of the m_axi_src interface next to the
other signals in the module definition.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2015-09-11 13:11:35 +02:00
parent 5aa11feb48
commit 89ceae3757
1 changed files with 4 additions and 2 deletions
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6
library/axi_dmac/axi_dmac.v
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@ -67,8 +67,6 @@ module axi_dmac (
// Master AXI interface
input m_dest_axi_aclk,
input m_dest_axi_aresetn,
input m_src_axi_aclk,
input m_src_axi_aresetn,
// Write address
output [31:0] m_dest_axi_awaddr,
@ -106,6 +104,10 @@ module axi_dmac (
input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata,
output m_dest_axi_rready,
// Master AXI interface
input m_src_axi_aclk,
input m_src_axi_aresetn,
// Read address
input m_src_axi_arready,
output m_src_axi_arvalid,