From 89f5d2394e9803595499d11c25dfe1dabfaa32fb Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 28 Apr 2016 15:46:27 -0400
Subject: [PATCH] altera- clock variations

---
 library/common/altera/ad_cmos_clk.v | 26 +++++---------------------
 library/common/altera/ad_lvds_clk.v | 12 +++++++-----
 2 files changed, 12 insertions(+), 26 deletions(-)

diff --git a/library/common/altera/ad_cmos_clk.v b/library/common/altera/ad_cmos_clk.v
index f5a344f65..652a9dd75 100644
--- a/library/common/altera/ad_cmos_clk.v
+++ b/library/common/altera/ad_cmos_clk.v
@@ -49,29 +49,13 @@ module ad_cmos_clk (
   input     clk_in;
   output    clk;
 
-  // wires
-
-  wire      clk_ibuf_s;
-
   // instantiations
 
-  IBUFG i_rx_clk_ibuf (
-    .I (clk_in),
-    .O (clk_ibuf_s));
-
-  generate
-  if (DEVICE_TYPE == VIRTEX6) begin
-  BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
-    .CLR (1'b0),
-    .CE (1'b1),
-    .I (clk_ibuf_s),
-    .O (clk));
-  end else begin
-  BUFG i_clk_gbuf (
-    .I (clk_ibuf_s),
-    .O (clk));
-  end
-  endgenerate
+  alt_clk i_clk (
+    .rst (1'b0),
+    .refclk (clk_in),
+    .outclk_0 (clk),
+    .locked ());
 
 endmodule
 
diff --git a/library/common/altera/ad_lvds_clk.v b/library/common/altera/ad_lvds_clk.v
index eab93e029..12937f03e 100644
--- a/library/common/altera/ad_lvds_clk.v
+++ b/library/common/altera/ad_lvds_clk.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -46,14 +44,18 @@ module ad_lvds_clk (
   clk);
 
   parameter   DEVICE_TYPE       = 0;
-  localparam  SERIES7       = 0;
-  localparam  VIRTEX6       = 1;
 
   input     clk_in_p;
   input     clk_in_n;
   output    clk;
   
-  assign clk = clk_in_p;
+  // instantiations
+
+  alt_clk i_clk (
+    .rst (1'b0),
+    .refclk (clk_in_p),
+    .outclk_0 (clk),
+    .locked ());
 
 endmodule