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altera- clock variations

main
Rejeesh Kutty 2016-04-28 15:46:27 -04:00
parent 243d3e6e41
commit 89f5d2394e
2 changed files with 12 additions and 26 deletions
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26
library/common/altera/ad_cmos_clk.v
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@ -49,29 +49,13 @@ module ad_cmos_clk (
input clk_in; input clk_in;
output clk; output clk;
// wires
wire clk_ibuf_s;
// instantiations // instantiations
IBUFG i_rx_clk_ibuf ( alt_clk i_clk (
.I (clk_in), .rst (1'b0),
.O (clk_ibuf_s)); .refclk (clk_in),
.outclk_0 (clk),
generate .locked ());
if (DEVICE_TYPE == VIRTEX6) begin
BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_ibuf_s),
.O (clk));
end else begin
BUFG i_clk_gbuf (
.I (clk_ibuf_s),
.O (clk));
end
endgenerate
endmodule endmodule

12
library/common/altera/ad_lvds_clk.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps `timescale 1ns/100ps
@ -46,14 +44,18 @@ module ad_lvds_clk (
clk); clk);
parameter DEVICE_TYPE = 0; parameter DEVICE_TYPE = 0;
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
input clk_in_p; input clk_in_p;
input clk_in_n; input clk_in_n;
output clk; output clk;
assign clk = clk_in_p; // instantiations
alt_clk i_clk (
.rst (1'b0),
.refclk (clk_in_p),
.outclk_0 (clk),
.locked ());
endmodule endmodule