altera- clock variations
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243d3e6e41
commit
89f5d2394e
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@ -49,29 +49,13 @@ module ad_cmos_clk (
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input clk_in;
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output clk;
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// wires
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wire clk_ibuf_s;
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// instantiations
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IBUFG i_rx_clk_ibuf (
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.I (clk_in),
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.O (clk_ibuf_s));
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generate
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if (DEVICE_TYPE == VIRTEX6) begin
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BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
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.CLR (1'b0),
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.CE (1'b1),
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.I (clk_ibuf_s),
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.O (clk));
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end else begin
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BUFG i_clk_gbuf (
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.I (clk_ibuf_s),
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.O (clk));
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end
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endgenerate
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alt_clk i_clk (
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.rst (1'b0),
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.refclk (clk_in),
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.outclk_0 (clk),
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.locked ());
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endmodule
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@ -34,8 +34,6 @@
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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@ -46,14 +44,18 @@ module ad_lvds_clk (
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clk);
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parameter DEVICE_TYPE = 0;
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localparam SERIES7 = 0;
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localparam VIRTEX6 = 1;
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input clk_in_p;
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input clk_in_n;
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output clk;
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assign clk = clk_in_p;
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// instantiations
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alt_clk i_clk (
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.rst (1'b0),
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.refclk (clk_in_p),
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.outclk_0 (clk),
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.locked ());
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endmodule
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