zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_ad9162: Updates for ad_dds phase acc wrapper

main
AndreiGrozav 2018-06-06 14:21:11 +03:00 committed by AndreiGrozav
parent 8cd88150f1
commit 8a306ce96b
5 changed files with 81 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
library/axi_ad9162/Makefile
View File

@ -5,9 +5,11 @@
LIBRARY_NAME := axi_ad9162
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_2.v
GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v

4
library/axi_ad9162/axi_ad9162.v
View File

@ -40,6 +40,7 @@ module axi_ad9162 #(
parameter ID = 0,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DAC_DATAPATH_DISABLE = 0) (
// jesd interface
@ -122,6 +123,9 @@ module axi_ad9162 #(
axi_ad9162_core #(
.ID (ID),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
i_core (
.dac_clk (dac_clk),

117
library/axi_ad9162/axi_ad9162_channel.v
View File

@ -38,8 +38,9 @@
module axi_ad9162_channel #(
parameter CHANNEL_ID = 32'h0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) (
// dac interface
@ -303,10 +304,11 @@ module axi_ad9162_channel #(
assign dac_dds_data_s[ 31: 16] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 15: 0] : dac_dds_data_i_s[ 31: 16];
assign dac_dds_data_s[ 15: 0] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 31: 16] : dac_dds_data_i_s[ 15: 0];
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_00 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -316,10 +318,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[15:0]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_01 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -329,10 +332,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[31:16]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_02 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -342,10 +346,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[47:32]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_03 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -355,10 +360,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[63:48]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_04 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -368,10 +374,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[79:64]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_05 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -381,10 +388,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[95:80]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_06 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -394,10 +402,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[111:96]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_07 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -407,10 +416,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[127:112]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_08 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -420,10 +430,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[143:128]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_09 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -433,10 +444,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[159:144]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_10 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -446,10 +458,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[175:160]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_11 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -459,10 +472,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[191:176]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_12 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -472,10 +486,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[207:192]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_13 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -485,10 +500,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[223:208]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_14 (
.clk (dac_clk),
.dds_format (dac_dds_format),
@ -498,10 +514,11 @@ module axi_ad9162_channel #(
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[239:224]));
ad_dds #(
ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
i_dds_15 (
.clk (dac_clk),
.dds_format (dac_dds_format),

8
library/axi_ad9162/axi_ad9162_core.v
View File

@ -38,8 +38,9 @@
module axi_ad9162_core #(
parameter ID = 0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) (
// dac interface
@ -101,6 +102,9 @@ module axi_ad9162_core #(
axi_ad9162_channel #(
.CHANNEL_ID (0),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_channel_0 (
.dac_clk (dac_clk),

2
library/axi_ad9162/axi_ad9162_ip.tcl
View File

@ -14,7 +14,7 @@ adi_ip_files axi_ad9162 [list \
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_dds_2.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \